System information

Watchdog Timer
VSBC-6 Reference Manual Reference – 39
Watchdog Timer
A watchdog timer circuit is included on the VSBC-6 to reset the CPU if proper software
execution fails or a hardware malfunction occurs.
E
NABLING THE
W
ATCHDOG
To enable or disable the watchdog, set or clear bit D0 in I/O port 0E0h (or 1E0h if selected in
CMOS Setup). When changing the contents of the register, make sure not to alter the value of the
other bits.
The following code example enables the watchdog:
in al,E0h
or al,01h
out E0h,al
Note! The watchdog timer powers up in a disabled state.
R
EFRESHING THE
W
ATCHDOG
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (250 ms minimum). Outputting a 5Ah to the Watchdog
Timer Hold-Off Register at 0E1h (or 1E1h if selected in CMOS Setup) resets the watchdog time-
out period, preventing the CPU from being reset for the next 250 ms. See page 56 for additional
information.
There is no provision for selecting a different timeout period using software.
The following code example refreshes the watchdog:
mov al,5Ah
out E1h,al