System information

Interfaces and Connectors
EPM-15 Reference Manual 33
LVDS FLAT PANEL DISPLAY CONNECTOR
The integrated LVDS Flat Panel Display in the EPM-15 is an ANSI/TIA/EIA-644-1995
specification-compliant interface. It can support up to 24 bits of RGB pixel data plus 3 bits of
timing control (HSYNC/VSYNC/DE) on the 4 differential data output pairs. The LVDS clock
frequency ranges from 25 MHz to 85 MHz.
The 3.3V power provided to pins 19 and 20 of J12 is protected by a 1 Amp fuse.
See Figure 8 for connector location information.
Table 9: LVDS Flat Panel Display Pinout
J12
Pin
Signal
Name
Function
1 GND Ground
2 NC No Connection
3 LVDSA3 Diff. Data 3 (+)
4 LVDSA3# Diff. Data 3 (–)
5 GND Ground
6 LVFSCLK0 Differential Clock (+)
7 LVDSCLK0# Differential Clock (–)
8 GND Ground
9 LVDSA2 Diff. Data 2 (+)
10 LVDSA2# Diff. Data 2 (–)
11 GND Ground
12 LVDSA1 Diff. Data 1 (+)
13 LVDSA1# Diff. Data 1 (–)
14 GND Ground
15 LVDSA0 Diff. Data 0 (+)
16 LVDSA0# Diff. Data 0 (–)
17 GND Ground
18 GND Ground
19 +3.3V Protected Power Supply
20 +3.3V Protected Power Supply