Specifications

Section-3 Operation
October 17, 2013
3‐4
Copyright©2013,HarrisBroadcast
WARNING:Disconnectprimarypower priortoservicing. 888‐2693‐004
Generally,theinformationfoundontheLPULCDmenuscanalsobefoundonthewebbrowserscreens.Forfurther
details,referto3.4,GUIIn
terface.
Note
Modulation and the feature key changes must be made via the web browser and cannot be made with the
LCD control panel.
TheLCDmenutreescanbefoundbelowinSections3.2 . 4,3.2.5,&3.2.6.Thevaluesshowninthetreearesamples
onlyandwillvarydependingonapplication.
3.2.4 LCDStatusMenuTree
Figure 3-3 UAX LCD Status Menu Screens
Status
ON-AIR DATA LINEAR: OK
DIG SIGNAL PATH MOD FPGA PROG: OK SUCCESS: 0
PFRU (PLL) PFRU FPGA PROG: OK MOD FPGA COMM: OK ATTEMPT: 0
UP/DOWN CONVERTER UDC CPLD COMM: OK PFRU COMM: OK MOD HPI: OK NON-LINEAR: OK
BATTERY BACK-UP BATBACKUP: PRESENT RF MUTE: OK EXT 1PPS: N/A DAC CLOCK: OK SUCCESS: 0
BAT PACK: OK LO LEVEL: 2344 EXT 10 MHz: N/A MOD CLOCK: OK ATTEMPT: 0
BAT CHARGING: YES IF LEVEL: 757 INT 1PPS: OK MOD 4X CLOCK:OK LSB: xx dB
+12VDC BAT: +12.1V RF LEVEL: 2484 54 MHz CLOCK: OK 25 MHz: ClOCK: OK USB:xx dB
AMBIENT: 44.8C 10 MHz CLOCK: OK 54 MHz: CLOCK: OK SNR: 0 dB
+12VDC: +11.5V IF PLL LOCK: OK DUC FPGA PROG: OK EVM: 0 %
+20VDC: +20.4V RF PLL LOCK: OK DUC FPGA COMM: OK
UC IF ATTEN: 2702 IF LO REF: 54MHz DUC INPUT BUF: OK
UC RF ATTEN: 852 GPS PWR: OK SRC BUF: OK
DC IF ATTEN: 2048 #SAT DETECT: 9 ADAPT DSP COM: OK
DC RF ATTEN: 740 LAT: N39.956 MOD FPGA: 49C
POST FILTER LEVEL: 0% LONG: W91.364 DUC FPGA: 47C
PRE-FILTER LEVEL: 93% GPS TIME: xx:xx:xx AMBIENT: 32C
DC SELECTION: PRE-FILTER +24VDC: +24.1V
+12VDC: +11.9V
+5VDC: +4.9V
+3.3VDC: +3.3V
+1.4VDC: +1.4V
-12VDC: -12.1V
TRANSMITTER I/O TCU PRESENT: ACTIVE
REVISIONS APPLICATION: RF MUTE: INACTIVE
FAULT LOG F/W, DESC, OCCUR TIME GUI: RTAC RESET: INACTIVE
LPU BLOCK
FWDPWR:30W BOOTLOADER: RTAC HOLD: INACTIVE
PA BLOCK #
FWDPWR:662W REFLD PWR: .1W DSP: EXCITER ON: ACTIVE
RFLD PWR: 2.8 W FWD PWR: 2W MOD FPGA: EXCITER OFF: INACTIVE
BLK INTERLOCK: OK BLK INTERLOCK: OK DUC FPGA: RESTRIKE COMMAND: INACTIVE
VSWR: OK VSWR: OK PFRU FPGA EXCITER ACTIVE: ACTIVE
RS485 COMMS: OK RS485 COMM: OK EXP FPGA: REMOTE CONTROL: DISABLED
FAN SPEED: 40% FAN SPEED: 20% FP FPGA: POWER CONTROL: AUTO
PS1-4: OK PS1: OK SIG CPLD: RF MUTE: INACTIVE
PA 1-4 INTERLOCK:OK PA1 INTERLOCK: OK UDC CPLD: RTAC RESET: INACTIVE
PA 1-4 48VDC: OK PA1 48VDC: OK TX IO CPLD: RTAC HOLD: ACTIVE
PA 1-4 A AMPS: 6.6A PA 1A AMPS: 1.2A INP OPT CPLD: EXCITER ON: INACTIVE
PA 1-4 B AMPS: 6.6A PA 1B AMPS: 1.2A MICRO BRD: EXITER OFF: INACTIVE
PA 1-4 TEMP: 58.1C PA1 TEMP: 33.6C SIG BRD: RESTRIKE COMMAND: INACTIVE
FAN 1-4: OK PS 2: OK PFRU BRD: EXCITER ACTIVE: ACTIVE
PA 2 INTERLOCK: OK UDC BRD: REMOTE CONTROL: DISABLED
PA 2 48VDC: OK FP BRD: POWER CONTROL: AUTO
PA 2A AMPS: 3.0A TX IO BRD:
PA 2B AMPS:3.0A INPUT OPT BRD:
PA 2 TEMP: 46.3C EXP BRD:
FAN 1-5: OK