Specifications

Section-4 Theory
October 17, 2013
4‐10
Copyright©2013,HarrisBroadcast
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4.3.6 UDCUpconverterandAmplifier
The140MHzIFsignalissenttotheupconvertercircuitoftheUDC(Up/DownConverter)board,whereitis
heterodyneduptotheon‐channelfrequencyandamplified.Theoutputlevelis20dBm(100mWaverage)inany
digitalmodeand23dBm(200mW)peakofsyncinan
yanalogmode.Theon‐channelRFsignalisoutputfromthe
modulatorportionoftheLPUthrougha50‐ohmSMAconnectorattherearoftheLPU.Thisoutputsignalissuitable
foramplificationinsubsequentamplifierstages(inthelowerpartoftheLPUandalsoin associatedPA
Bs).
4.3.7 UDCDownconverter
TheRTACcircuitsinthesignalprocessingboardrequirevarioussamplesofthetransmitteroutputsignaltoperform
theirfunction.Thesesamplesmustbedownconvertedtothe140MHzIFfrequencyanddigitizedinordertopermit
adirect1:1comparisonwiththeideal(non‐distorted)digitallymodulatedsignalcomingfromthemodul
atorFPGA.
BecausetheRT
ACsystemrequiresmultiplesamples(pre‐filter,post‐filter,etc)andthereisonlyonedownconverter,
thesamplesareselectivelyprocessedone‐at‐a‐timebyafourpoleelectronicswitchattheinputofthe
downconverter.ThepositionoftheinputswitchandanRFattenuatortooptimizethesamplele
velsareboth
controlledbyfeedbackfromthesignalprocessingboard.
4.3.8 PreciseFrequencyReferenceUnit(PFRU)Board
ThePFRU(PreciseFrequencyReferenceUnit)boardperformsfourbasicfunctionsthroughfourcircuits:
• 10MHzreferenceoscillator
• 1stLOPLL
• 2ndLOPLL
• ProvidesforanoptionalGPSunit
Theco
reofthePRFUisthe10MHzreferenceoscillator,whichservesasthereferenceforthe1stand2
nd
LO
oscillators.Whenrequired,the10MHzreferenceosci llatormaybelockedtooneoftheseprecisefrequency
references:
• A1ppssignalcomingfromanoptionalinternalGPSreceiver
• A1ppssignalcomingfromanexternalprecisionsource
• A10MHzsignalcomingfromanexternalprecisionsource
Whenop
eratingintheMFNmode(i.e.non‐SFN)theLPUcanaccepta10MHz,1pps,orGPSfrequencyreference
inputviarear‐panelconnectors.Theseexternalreferencesmaybeusedwhenevergreaterfrequencyprecisionand/
oraprecisefrequencyoffsetarerequired.
Whenop
eratingintheSFNmode,anexternal1ppsorGPSinputisgenerallyalwaysrequired.
The1s
tLOPLLoscillatorprovidesaclocktotheIFDAC(DigitaltoAnalogConverter)toproducea140MHzanalogIF
outputfromthesignalprocessorboard.Theexactclockfrequencyvariesaccordingtomodulationformat,but
generallyfallsintherangeof409MHzto460MHz.Themodula
torandDUCFPGAsoperateatfrequencythatis
equaltotheDACclockdividedbyfour.
The2
nd
LOPLLoscillatorprovidesanRFcarriertotheupconverteranddownconverterportionsoftheUDCboard
forthesignalheterodyningprocess.
ThePFRUboar
dmayincludeanoptionalGPSreceiver.TheantennainputforthereceiverisconnectorJ8onthe
PFRUboard.A50ohmcoaxconnectsthisconnectortotheGPSantennainputSMAconnectorontheLPUrear
panel.TheGPSreceiverprovidesa1ppsprecisetimeandfr
equencyreferenceforSFNandprecisefrequency
control,asdescribedpreviously.
4.3.9 LVPSBoard971‐0035‐007
ThelowvoltagepowersupplyfortheLPUmodulatorsectionismountedtotheleftinsidewalloftheLPUchassis.
Thefollowingitemsaremountedonthepowersupplyboard.
• TheACInputconnector.
• A+5V,+24V,and‐12Vswitchingpowersupply,mountedtowardstherearofthepowersupplyboard.
• A+12Vswitchingpowersupply,mountedinthecenterofthepowersupplyboard.
• Provisionforanoptionalbatterybackupboard,mountedatthefrontofthepowersupplyboard.