Specifications

SPEC No.
LC99213A
MODEL No.
LM10V332
PAGE
13
Because of the characteristics of CMOS driver LSI, the power consumption of the display
module goes up with the clock frequency of XCK.
To minimize data transfer speed of XCK clock the LSI has the system of transferring 8 bit
parallel data through the 8 lines of shift registers.
Thanks to this system the power consumption of the display module is minimized.
In this circuit configuration, 8 bit display data shall input to data input pins of DU0-7 and
DL0-7.
Furthermore, the display module has bus line system for data input to minimize the power
consumption with data input terminals of each driver LSI being activated only when
relevant data input is fed.
Data input for column electrodes and chip select of driver LSI are made as follows:
The driver LSI at the left end of the display face is first selected, and the adjacent driver
LSI right next side is selected when data of 240 dot (30XCK) is fed. This process is
sequentially continued until data is fed to the driver LSI at the right end of the display
face. This process is followed simultaneously both at the top and bottom column drivers
LSI’s.
Thus data input will be made through 8 bit bus line sequentially from the left end of the
display face.
Since this display module contains no refresh RAM, it requires the above data and timing
pulse inputs even for static display.
The timing chart of input signals are shown in fig. 3 and Table 7.