Service manual
QT-CD250H/W
– 25 –
IC51 VHiLC72121/-1: Electronic Tuning (LC72121) (2/2)
15 Local oscillation, Signal input AMIN Input Serial data input: AMIN is selected when DVS = 0 is set.
When serial data input SNS = 1 is set:
Input frequency is 2-40 MHz.
Signal is sent to the swallow counter directly.
Dividing number to be set is 272- 65535. The actual dividing number
is the same as the setting value.
When serial data input SNS = 0 is set.
Input frequency is 0.5-10 MHz.
Signal is transferred to the 12-bit programmable divider directly.
Dividing number to be set is 4-4095. The actual dividing number is
the same as the setting value.
16 Local oscillation, Signal input FMIN Input Serial data input: FMIN is selected when DVS = 1 is set.
Input frequency is 10-160 MHz.
Signal is transferred to the swallow counter through the built-in
prescaler (1/2).
Dividing number to be set is 272-65535. The actual dividing number
is twice as the setting value because there is a built-in prescaler(1/2).
17 Power supply VDD — Power supply terminal for LC72121 (VDD = 2.7-3.5 V).
Power on reset circuit works when POWER ON.
18 Charge pump output PD Output Charge pump output terminal for PLL.
When the local oscillation signal frequency divided by N is higher
then the refernce frequency, "H" level is sent from the PD terminal.
When it is lower, "L" level is sent. When the frequencies are the
same, they become high impedance.
19 L.P.F. Amplifier transistor AIN Input L.P.F. Amplifier transistor
20 L.P.F. Amplifier transistor AOUT Output L.P.F. Amplifier transistor
21 Ground VSSA — Ground terminal for the low-pass filter MOS transistor of LC72121.
22 Xtal XOUT Output Crystal oscillator connection.(4.5 MHz/7.2 MHz)
Port Name
Terminal
Name
Pin No.
Input/Output
Function
Figure 25 BLOCK DIAGRAM OF IC
2
3
4
5
1
7
8
9
6
12
13
14
15
11
17
18
19
10
16
22
21
20
REFERENCE
DIVIDER
PHASE DETECTOR
CHARCE PUMP
UNLOCK
DETECTOR
UNIVERSAL
COUNTER
DATA SHIFT REGISTER
LATCH
12bits PROGRAMMABLE
DIVIDER
SWALLOW COUNTER
1/16, 1/17 4bits
1/2
CCB
I/F
POWER
ON
RESET
PD
AIN
AOUT
VSSa
IFIN
BO1 BO2 BO3 BO4 IO1 IO2
AMIN
FMIN
CE
DI
CL
DO
V
DD
VSSd
XOUT
XIN
VSSx