Specifications

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currently beyond the capabilities of
DASMx
. For this reason, it is advised that
code threading be not used if the size of the 8048 source image exceeds 2 Kbytes. If
images greater than this are disassembled, even with threading disabled, some
errors in automatically generated labels may be expected.
Intel MCS-51™ family (8051 etc.)
Intel introduced the 8051 to provide an upgrade path from the 8048. It would do
all that the 8048 would do and more. The heritage of the 8048 is obvious in the
architecture and instruction set of the 8051.
Like the 8048, the 8051 was initially available in a number of variants (e.g. 8031 and
8751). Subsequently, many further variants of the 8051 have been produced by
Intel and by other manufacturers. Some of these added to the instruction set.
DASMx
will only correctly disassemble code for the original 8051 devices that
shared the MCS-51™ instruction set.
Signetics 2650
The Signetics 2650 is a rather oddball processor when compared to most other
processors handled by
DASMx
. It operates on 8-bit data and can address 32,768
bytes of memory organised in four pages of 8,192 bytes each. It has a large range
of addressing modes, made possible by the use of bits encoded in the second byte
of two and three byte instructions. It has a 3-bit stack pointer which means that
subroutines can be nested to, at most, eight deep.
Assembler pseudo operations
Assembler pseudo operations (e.g. that to define a data word) are not in a standard
style that matches the chosen processor. The pseudo-ops are common across all
processor disassembly output. In general, the pseudo-ops follow Intel
conventions:
❏ the ';' character to denote a comment;
❏ the ':' character following a label;
❏
db
, to define a data byte, character or string;
❏
dw
, to define a data word;
❏
org
, to specify a starting address.
If these do not suit your preferred assembler, then use of search and replace in a
text editor can probably effect the required changes.