User`s guide

1/15/03 9-1
Chapter 9
Watchdog Timer
The Watchdog Timer can be used to detect a ‘hung’ system and reset it, causing it to
resume operation. If enabled, the Watchdog Timer will reset the system when it counts
down to zero. The system software prevents this from occurring by periodically reloading
the Watchdog Timer as part of a timer interrupt routine. If the software ceases functioning,
the Watchdog Timer will not be reloaded before counting down to zero, and the system will
be reset.
9.1 Theory of Operation
The Watchdog Timer is implemented as two cascaded count-down timers, a prescale
timer, which cannot be read by software, and an 8-bit Watchdog Timer. The prescale timer
reloads automatically each time it counts down to zero, using a value specified in the
WTCTL.WDTPR field. The Watchdog Timer also has a reload value, which is set by writing
the WDCNT register as part of Watchdog initialization.
Each time the prescale timer counts down to zero, the Watchdog Timer is decremented. A
Watchdog reset occurs if both the Watchdog Timer and the prescale timer are zero, and
the Watchdog Timer Enable bit (WDCTL.WDTEN) is set.
The Watchdog Timer is reloaded whenever the WTCTL.WDTRL bit is cleared and then set
within 32 CCLK periods. If an interrupt occurs between the two writes, the operation may
not succeed. The two writes can be followed by a read of the WDCNT register to see if it
has been reloaded. If not, the writes to the WTCTL.WDTRL bit can be attempted again.
The Watchdog Timer is disabled following a reset, including those it asserts itself.
9.1.1 Setting the Timer Interval
The Watchdog interval depends on the prescaler value, the TIMEOUT reload value, and
the PCLK frequency:
Watchdog interval(s) = prescaler × (reload + 1)/PCLK (Hz)
For example, with a prescaler value of 32,768, a reload value of 256, and a PCLK of
20 MHz, the interval would be (to three significant figures) 0.421 seconds.