User`s guide

LZ87010 Advance User’s Guide Enhanced Timers
1/15/03 8-21
8.3.7 T(x)STA (Timer Status) Registers
The T(x)STA (timer status) registers contain status bits for the individual interrupt sources in
the Timer unit. These bits are set when the corresponding condition occurs, regardless of
whether the interrupt is enabled. Bits in this register remain set until cleared by software.
Clearing a bit also clears the associated interrupt. Setting a bit does not cause an interrupt.
Table 8-27. T(x)STA Register
BIT 7 6 5 4 3 2 1 0
FIELD /// /// /// OVF_ST CMP1_ST CMP0_ST CAP1_ST CAP0_ST
RESET 00000000
RW RW RW RW RW RW RW RW RW
ADDR
Timer 2: 0xD2
Timer 3: 0xE2
Timer 4: 0xF2
Timer 5: 0xA2
Table 8-28. T(x)STA Register Bits
BIT NAME DESCRIPTION
7:5 /// Reserved Reads ‘0’, write ‘0’.
4OVF_STOverflow Status Set to ‘1’ when the timer rolls over to zero.
3 CMP1_ST Compare 1 Status Set to ‘1’ when the Compare 1 value matches the count.
2 CMP0_ST Compare 0 Status Set to ‘1’ when the Compare 0 value matches the count.
1 CAP1_ST
Capture 1 Status
Timer 2 and Timer 3: Set to ‘1’ when the Capture 1 unit is triggered.
Timer 4 and Timer 5: Reserved.
0 CAP0_ST
Capture 0 Status
Timer 2 and Timer 3: Set to ‘1’ when the Capture 0 unit is triggered.
Timer 4 and Timer 5: Reserved.