User`s guide
Enhanced Timers LZ87010 Advance User’s Guide
8-20 1/15/03
8.3.6 T(x)CON (Timer Configuration) Registers
The T(x)CON (timer configuration) registers set up the timers, with input clock source, input
clock divider, enable/disable/clear control, and overflow interrupt enable fields. The timer
should be stopped first (by setting the T(x)CON.CS field to zero) before other changes are
made.
Table 8-25. T(x)CON Register
BIT 7 6 5 4 3 2 1 0
FIELD CLK_SEL[1] CLK_SEL[0] CS OVF_EN CCL DIV[2] DIV[1] DIV[0]
RESET 0 0 000000
RW RW RW RW RW RW RW RW RW
ADDR
Timer 2: 0xD1
Timer 3: 0xE1
Timer 4: 0xF1
Timer 5: 0xA1
Table 8-26. T(x)CON Register Bits
BIT NAME DESCRIPTION
7:6 CLK_SEL[1:0]
Clock Select Selects the input clock, which is then divided by the clock
divisor selected in the DIV[2:0] field. This field should not be changed un-
less the timer is stopped.
00 = PCLK
01 = CLK_SUB
10 = Timer 2: TM3CMP1, Timer4: TM5CMP1, Others: Reserved
11 = CTIN(x)
5CS
Counter Start
0 = Stop count
1 = Start count
4OVF_EN
Overflow Interrupt Enable
0 = No interrupt request occurs when counter overflow
1 = Interrupt request occurs when counter overflows
3 CCL
Clear Count Setting this bit to ‘1’ clears the contents of the counter to
0x0000. The bit is reset to ‘0’ automatically when the counter is cleared.
2:0 DIV[2:0]
Clock Divider These bits select the divisor for this timer. The source
for the clock is determined by CLK_SEL. This field should not be
changed unless the timer is stopped.
000 = CLK
001 = CLK ÷ 2
010 = CLK ÷ 4
011 = CLK ÷ 8
100 = CLK ÷ 16
101 = CLK ÷ 32
110 = CLK ÷ 64
111 = CLK ÷ 128 (Timer 2 and Timer 4)
111 = CLK ÷ 32,768 (Timer 3 and Timer 5)