User`s guide

Enhanced Timers LZ87010 Advance User’s Guide
8-18 1/15/03
8.3.4 T(x)CMP[1:0][H:L] (Compare Data) Registers
There are 16 Compare Data registers (four timers times two compare units times two reg-
isters per compare unit): T2CMP0H, T2CMP0L, T2CMP1H, T2CMP1L, T3CMP0H,
T3CMP0L, T3CMP1H, T3CMP1L, T4CMP0H, T4CMP0L, T4CMP1H, T4CMP1L,
T5CMP0H, T5CMP0L, T5CMP1H, T5CMP1L. All are read/write registers.
Half of these registers are low-byte registers (with names ending in ‘L’), which contain the
lower 8 bits of the compare value. Half are high-byte registers (with names ending in ‘H’),
which contain the upper 8 bits of the compare value.
NOTE: Always write the LSB first, then the MSB. See Section 8.2.2.
Table 8-19. T(x)CMP0H Registers
BIT 7 6 5 4 3 2 1 0
FIELD CMP0[15] CMP0[14] CMP0[13] CMP0[12] CMP0[11] CMP0[10] CMP0[9] CMP0[8]
RESET 11111111
RW RW RW RW RW RW RW RW RW
ADDR
T2CMP0H: 0xD5
T3CMP0H: 0xE5
T4CMP0H: 0xF5
T5CMP0H: 0xA5
Table 8-20. T(x)CMP0L Registers
BIT 7 6 5 4 3 2 1 0
FIELD CMP0[7] CMP0[6] CMP0[5] CMP0[4] CMP0[3] CMP0[2] CMP0[1] CMP0[0]
RESET 11111111
RW RW RW RW RW RW RW RW RW
ADDR
T2CMP0L: 0xD4
T3CMP0L: 0xE4
T4CMP0L: 0xF4
T5CMP0L: 0xA4
Table 8-21. T(x)CMP1H Register
BIT 7 6 5 4 3 2 1 0
FIELD CMP1[15] CMP1[14] CMP1[13] CMP1[12] CMP1[11] CMP1[10] CMP1[9] CMP1[8]
RESET 11111111
RW RW RW RW RW RW RW RW RW
ADDR
T2CMP1H: 0xD7
T3CMP1H: 0xE7
T4CMP1H: 0xF7
T5CMP1H: 0xA7
Table 8-22. T(x)CMP1L Register
BIT 7 6 5 4 3 2 1 0
FIELD CMP1[7] CMP1[6] CMP1[5] CMP1[4] CMP1[3] CMP1[2] CMP1[1] CMP1[0]
RESET 11111111
RW RW RW RW RW RW RW RW RW
ADDR
T2CMP1L: 0xD6
T3CMP1L: 0xE6
T4CMP1L: 0xF6
T5CMP1L: 0xA6