User`s guide

Enhanced Timers LZ87010 Advance User’s Guide
8-10 1/15/03
Table 8-3. Compare Function
TIMER SIGNAL
OUTPUT
POLARITY
REGISTERS STATUS BIT
INTERRUPT
ENABLE
OUTPUT
ENABLE
2
CTCMP2A T2CMP.CMP0[1:0]
T2CMP0H,
T2CMP0L
T2STA.CMP0_ST T2CMP.IOE0
TCMPOE[7]
CTCMP2B T2CMP.CMP1[1:0]
T2CMP1H,
T2CMP1L
T2STA.CMP1_ST T2CMP.IOE1 TCMPOE[6]
3
CTCMP3A T3CMP.CMP0[1:0]
T3CMP0H,
T3CMP0L
T3STA.CMP0_ST T3CMP.IOE0 TCMPOE[5]
CTCMP3B T3CMP.CMP1[1:0]
T3CMP1H,
T3CMP1L
T3STA.CMP1_ST T3CMP.IOE1 TCMPOE[4]
4
CTCMP4A T4CMP.CMP0[1:0]
T4CMP0H,
T4CMP0L
T4STA.CMP0_ST T4CMP.IOE0 TCMPOE[3]
CTCMP4B T4CMP.CMP1[1:0]
T4CMP1H,
T4CMP1L
T4STA.CMP1_ST T4CMP.IOE1 TCMPOE[2]
5
CTCMP5A T5CMP.CMP0[1:0]
T5CMP0H,
T5CMP0L
T5STA.CMP0_ST T5CMP.IOE0 TCMPOE[1]
CTCMP5B T5CMP.CMP1[1:0]
T5CMP1H,
T5CMP1L
T5STA.CMP1_ST T5CMP.IOE1 TCMPOE[0]
Table 8-4. Output Polarity for Compare Pins
T(x)CMP.CMP(y)[1:0] DESCRIPTION
00 No change in output state.
01
Output pin driven LOW during compare match and
HIGH otherwise.
10
Output pin driven HIGH during compare match and
LOW otherwise.
11
Output pin toggled on compare match and held
steady between matches.