User`s guide

8051-Compatible Timers LZ87010 Advance User’s Guide

7-2 1/15/03

Each timer has a Timer Run bit that acts as a timer enable. The Timer Run bit is

TCON.TR0 for Timer 0 and TCON.TR1 for Timer 1. The timer will not run unless the Timer

Run bit is set. A second bit, the Gate bit (TMOD.GATE0 or TMOD.GATE1), determines

whether the timer runs continuously or is gated by an external signal (INT[0] or INT[1]). If

Gate is ‘0’ and Timer Run is ‘1’, the timer will run continuously. If Gate is ‘1’ and Timer Run

is ‘1’, The timer will only run when the interrupt input is HIGH. This allows the timer to mea-

sure pulse widths on the INT(x) pins.

When a timer overflows (rolls over to zero), it sets an interrupt flag and can optionally gen-

erate an interrupt. The interrupt flags are in TCON.IF0 and TCON.IF1. Interrupts are

enabled in the IE (interrupt enable) register: IE[0] for Timer 0 and IE[1] for Timer 1.

Each timer has a dedicated interrupt vector: 0x000B for Timer 0, and 0x001B for timer 1.

7.1.1 Timer Modes

There are four basic modes of operation: Mode 0 through Mode 4. In all modes,

the timers count up.

7.1.1.1 Mode 0

Mode 0 is a 13-bit free-running mode. The high 8 bits of the count are in TH(x) (that is, TH0

for Timer 0 and TH1 for Timer 1), and the low 5 bits of the count are in TL(x)[4:0]. Bits

TL(x)[7:5] are undefined. With a 20 MHz PCLK, the counter will overflow every 0.4096 ms

(2,441 Hz). See Figure 7-2.

Figure 7-2. Timer Mode 0

LZ87010-101

TH(x) TL(x)

TCON.TF(x)

TO INTERRUPT

CONTROLLER

f[12:5] f[4:0]

XXX

CLKTCLK(x) OVF

n[12:0]

f(n) = n+1

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