User`s guide

LZ87010 Advance User’s Guide I/O Ports
1/15/03 6-5
6.3 Registers
6.3.1 General-Purpose I/O Registers
The general-purpose I/O registers sample external I/O pins when read by the processor and
drive external I/O pins when written by the processor. These bits are set to ‘1’ on Reset (with
the exception of PORT3[7:6], which are set to ‘0’) to set the pins HIGH, which is the state that
allows the pins to function as inputs. The HIGH state also minimizes power consumption.
The PORT0, PORT1, ... PORT8 registers are also called the P0, P1, ... P8 registers.
NOTE: *On PORT3 only, bits [7:6] (which are shared with the I
2
C pins SCL and SDA) are zero on Reset.
Table 6-2. PORT0, PORT1, PORT3, PORT5, PORT6, PORT7, PORT8 Registers
BIT 7 6 5 4 3 2 1 0
FIELD D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
RESET 1* 1* 111111
RW RW RW RW RW RW RW RW RW
ADDR
PORT0: 0x80
PORT1: 0x90
PORT3: 0xB0
PORT5: 0x91
PORT6: 0xC0
PORT7: 0xD8
PORT8: 0x93
Table 6-3. General-Purpose I/O Register Bits
BIT NAME DESCRIPTION
7:0 D
Data When this field is read, the input pins will be sampled, and the register state
will be updated to reflect the state of the pins (active HIGH logic; a HIGH signal will
result in a ‘1’ bit in the register). Those I/O ports that are bit-addressable (Ports 0,
1, 3, 6, and 7) can be updated one bit at a time. When this field is written, the state
of the pins will be updated to match the state of the register. To put bits into a high-
impedance state suitable for being used as inputs, ‘1’ bits should be written prior to
reading. Otherwise, bus contention will result.