User`s guide

System Clocking LZ87010 Advance User’s Guide
2-6 1/15/03
2.3 Registers
2.3.1 CLKCFG (Clock Configuration) Register
The CLKCFG (Clock Configuration) register determines the active system clock, the cur-
rent system clock divider, and the current ADC clock divider.
Table 2-2. CLKCFG (Clock Configuration) Register
BIT 7 6 5 4 3 2 1 0
FIELD CLKSEL /// CLKADC[2] CLKADC[1] CLKADC[0] CLKDIV[2] CLKDIV[1] CLKDIV[0]
RESET 001 0 1 000
RW RW RW RW RW RW RW RW RW
ADDR 0x94
Table 2-3. CLKCFG Register Fields
BIT NAME DESCRIPTION
7CLKSEL
Clock Select Selects the oscillator used for the system clocks (CCLK, SCLK,
and PCLK). When ‘1’, the core clock source is the 32 kHz subclock (SUBCLK)
oscillator, when ‘0’ it is the high-frequency (HFCLK) oscillator. The selected
clock is divided as specified in the CLKDIV[2:0] field to generate CCLK and
SCLK. SCLK is divided by 2 to generate PCLK.
6 /// Reserved Reads return 0; writes are ignored.
5:3 CLKADC
A/D Converter Clock Divider The ADC clock (ADCCLK) is derived from the
high-frequency oscillator (HFCLK) by dividing it as specified in this field, which is
decoded as shown in Table 2-4.
2:0 CLKDIV
Clock Divider CCLK and SCLK are generated by dividing HFCLK by a value
encoded in the CLKDIV[2:0] field. The encoding is shown in Table 2-5.
Table 2-4. CLKADC[2:0] Encoding
CLKADC[2:0] DIVIDE HFCLK BY
000 1
011 3
100 4
Others 5
Table 2-5. CLKDIV[2:0] Encoding
CLKDIV[2:0] DIVIDE CLOCK BY
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128