User`s guide

System Clocking LZ87010 Advance User’s Guide
2-2 1/15/03
2.1.1 Internal Clocks
Internal clocking is shown in Figure 2-2. The individual clock signals are described here.
2.1.1.1 HFCLK
This is the output of the high-frequency oscillator on the XTAL1 and XTAL2 pins. It is used
by the ADC and the system clock generator. HFCLK halts in Stop mode.
2.1.1.2 SUBCLK
This is the output of the 32 kHz subclock oscillator on the XTAL_SUB1 and XTAL_SUB2
pins. It provides a low-frequency clock for the enhanced timer units and can be used as the
system clock when low-frequency operation is desired. The subclock halts in Stop mode.
2.1.1.3 CCLK
The LZ87010 allows software to choose whether HFCLK or SUBCLK will be used as the
processor core clock. The selected clock is divided by a software-selectable value (chosen
from: 1, 2, 4, 8, 16, 32, 64, or 128). The resulting clock is called CCLK (Core Clock) and
has a duty cycle of 50%. See Figure 2-2. CCLK halts in Idle and Stop modes.
2.1.1.4 SCLK
SCLK (State Machine Clock), runs at the same frequency as CCLK, but, unlike CCLK, it is
not halted in Idle mode. Instead, it halts only in Stop mode. SCLK is used for internal state
machines that are not visible to the user.
2.1.1.5 PCLK
PCLK (Peripheral Clock) is used to clock most of the peripherals in the LZ87010. PCLK
always runs at half the speed of SCLK. It halts only in Stop mode.
2.1.1.6 ADCCLK
The ADC Clock (ADCCLK) is derived from HFCLK, and can be divided by 1, 3, 4, or 5. For
proper ADC operation, the ADC clock divider should be selected to run ADCCLK within the
range given in the AC Specifications. ADCCLK halts only in Stop mode.