User`s guide

LZ87010 Advance User’s Guide Introduction
1/15/03 1-9
1.6.2 Program Memory
Program memory is a 64K × 8 Flash array. On Reset, execution begins at Flash memory
address 0. Program memory can also be used for read/write data storage.
This memory is shipped from the factory with all bytes set to 0xFF. Initial programming
takes place under the control of either an external bulk programmer or the debug interface.
Subsequent reprogramming can be controlled by an external bulk programmer, a boot-
strap loader or the debug interface. Both sector erase and mass erase functions are sup-
ported (sectors are 512 bytes).
A security feature allows the program memory interface to be read-protected if desired,
preventing its contents from being downloaded via the debug interface.
1.6.3 Internal Data RAM
The internal data RAM consists of 256 bytes of static RAM. The processor’s direct and indi-
rect addressing modes can access the lower 128 bytes of RAM, while the upper 128 bytes
of RAM can be accessed by the indirect addressing mode only.
1.6.4 MOVX Data RAM
An additional 4KB of static RAM is provided on the chip and is accessible through the
MOVX instruction.
1.6.5 SHARP Debug Interface
The debug interface uses a two-wire serial data channel to connect with external debug-
ging hardware. Internally, it provides single-step support, start/stop control, breakpoint
memory, trace memory, and read/write access to registers and memory. The internal
Flash memory can be programmed over this interface. The pins of the debug interface are
also used for manufacturing testing. See Figure 1-4.
Figure 1-4. Sharp Debug Interface
DEBUG
MODE CONTROL
TRACE CONTROL
TRACE MEMORY
TEST
BREAKPOINT CONTROL
BREAKPOINT MEMORY
SHARP DEBUG
INTERFACE
SDI_DATA
SDI_CLK
LZ87010-65
INTERNAL TO
THE LZ87010
EXTERNAL TO
THE LZ87010