User`s guide

Introduction LZ87010 Advance User’s Guide
1-4 1/15/03
1.4 Block Diagram
Figure 1-2. LZ87010 Block Diagram
LZ87010-63
PORT 0,
INTERRUPTS
PORT 1 [7:6],
EXTERNAL
MEMORY R/W
PORT 1 [5:0],
TIMER 3
PORT 5,
EXTERNAL
MEMORY DATA
PORT 8,
EXTERNAL
MEMORY
ADDRESS
PORT 9
PORT 6 [7:4],
TIMER 5
PORT 6 [3:0],
TIMER 4
PORT 2,
EXTERNAL
MEMORY
ADDRESS
PROGRAM
MEMORY
64KB FLASH
8051-
COMPATIBLE
CPU
DEBUG
INTERFACE
MOVX
DATA RAM
4,096 BYTES
INTERNAL
DATA RAM
256 BYTES
DAC1
WAVETABLE
128 BYTES
CLOCKING
RESET, WATCHDOG
TIMER
DIGITAL 3.3 V POWER
DIGITAL 2.5 V POWER
ANALOG 3.3 V POWER
REGULATOR ENABLE
DIGITAL GROUND
ANALOG GROUND
DAC1
ADC
12 BITS
PORT 3 [5:4],
WAVEFORM
GENERATOR
CLOCK
PORT 3 [7:6],
I
2
C
PORT 3 [3:2],
UART1
PORT 3 [1:0],
UART0
PORT 7 [7:6],
TIMERS 1 and 0
PORT 7 [5:0],
TIMER 2
P3[3], RXD1
P3[2], TXD1
P3[5], WFGIN0
P3[4], WFGIN1
P3[7], SDA
P3[6], SCL
P3[1], TXD0
P3[0], RXD0
P0[7:0], INT[7:0]
P1[7], nPSEN
P1[6], nPSWR
P1[5], CTCMP3B
P1[4], CTCMP3A
P1[3], CTCAP3B
P1[2], CTCAP3A
P1[1]
P1[0], CTIN3
P2[7:0], XMA[15:8]
P6[7], CTCMP5B
P6[6], CTCMP5A
P6[5]
P6[4], CTIN5
P6[3], CTCMP4B
P6[2], CTCMP4A
P6[1]
P6[0], CTIN4
XTAL2
XTAL1
XTAL_SUB2
XTAL_SUB1
SDI_CLK
SDI_DATA
VDD
VDD_CORE
VDDA
ENDC
VSS
VSSA
RESET
P7[7], CTIN1
P7[6], CTIN0
P7[5], CTCMP2B
P7[4], CTCMP2A
P7[3], CTCAP2B
P7[2], CTCAP2A
P7[1]
P7[0], CTIN2
DA0
DA1
AN[7:0]
DAVREF
ADVREF
P5[7:0], XMD[7:0]
P8[7:0], XMA[7:0]
P9[7:0]
DAC0
WAVETABLE
128 BYTES
DAC0