User`s guide

LZ87010 Advance User’s Guide Preface
1/15/03 xv
Terms and Conventions
Multiplexed Pins
The LZ87010 is manufactured in an LQFP package with 100 pins. Some pins have only
one function, but others support two functions. These multiplexed pins have both functions
available simultaneously.
Pin Names
Package pins are named to indicate the signal(s) or functionality available at the pin. If the
signal or function is active LOW, the name is prefixed with a lower-case ‘n’, such as
nPSWR. Multiplexed pins are named to indicate all available functions, such as Pin 80:
P0[5]/INT[5], which can function as either General-Purpose I/O Port 0, bit 5, or Interrupt
Request bit 5.
These naming conventions help designers recognize and avoid collisions between multiplexed
functions but can complicate explanatory text, so this Guide uses the name appropriate to the
context. A discussion of an interrupt, for example, would refer to signal INT[5], but information
about Port 0 bit 5 would use P0[5]. Readers must be aware that these are separate signals,
with distinctly different functionality, which happen to be available on the same pin.
Peripheral Devices
The LZ87010 is an 8-bit microcontroller using an 8051-compatible architecture. Additional
functionality not available in the standard 8051 consists mostly of additional peripheral
devices not present in the 8051. These devices have their I/O and control registers
mapped to the ‘Special Function Register’ (SFR) memory space of the 8051 architecture,
which is in the data memory address range of 0x80-0xFF.
Register Addresses
The LZ87010 is a memory-mapped device with programmable, internal registers that con-
trol its operation. Each internal register is located at a unique address in the memory map.
In this Guide, the addresses for all registers are expressed as an absolute hex address.