User`s guide

I
2
C Interface
15-8 1/15/03
15.4.5 ICHCNT (I
2
C Clock High Time) Register
The ICHCNT register sets the period for the serial clock HIGH time.
Table 15-12. ICHCNT Register
BIT 7 6 5 4 3 2 1 0
FIELD H_CNT[7] H_CNT[6] H_CNT[5] H_CNT[4] H_CNT[3] H_CNT[2] H_CNT[1] H_CNT[0]
RESET 00000000
RW RW RW RW RW RW RW RW RW
ADDR 0xBC
Table 15-13. ICHCNT Register Bits
BIT NAME DESCRIPTION
7:0 H_CNT[7:0]
High Count This register sets the SCL HIGH period. The HIGH period
will be ICHCNT + 3 PCLK periods in 100 kbit/s mode, and ICHCNT + 4
PCLK cycles in 400 kbit/s mode. The ICHCNT Register must be set before
any I
2
C bus transaction can take place to insure proper I/O timing.