User`s guide
I
2
C Interface
15-6 1/15/03
15.4.3 ICUSAR (I
2
C Upper Slave Address) Register
The ICUSAR (I
2
C Upper Slave Address) Register holds the upper 2 address bits in 10-bit
addressing mode, plus a data direction (R/W) bit. This register is not used in Master mode.
Table 15-8. ICUSAR Register
BIT 7 6 5 4 3 2 1 0
FIELD U_AR[4] U_AR[3] U_AR[2] U_AR[1] U_AR[0] S_ADDR[9] S_ADDR[8] R/W
RESET 11110000
RW RW RW RW RW RW RW RW RW
ADDR 0xB6
Table 15-9. ICUSAR Register Bits
BIT NAME DESCRIPTION
7:3 U_AR[4:0] Upper Address Bits Must be set to ‘0b11110’.
2:1 S_ADDR[9:8]
Slave Address[9:0] The upper 2 bits of the 10-bit slave address. Not
used in 7-bit addressing mode.
0RW
Slave Read/Write In 10-bit Slave mode, this provides read/write con-
trol for data transfers:
0 = Write
1 = Read