User`s guide

I
2
C Interface
15-4 1/15/03
15.4 Registers
15.4.1 ICCON (I
2
C Configuration) Register
The ICCON register sets the operating mode of the interface and contains the flags used
to start a transfer and to set the data direction.
Table 15-4. ICCON Register
BIT 7 6 5 4 3 2 1 0
FIELD RS_P_N R_W_N_CTRL P_TRNSFR S_TRNSFR FS_STD_N I2C_EN MODE[1] MODE[0]
RESET 0 0 0 0 1 000
RW RW RW RW RW RW RW RW RW
ADDR 0xB4
Table 15-5. ICCON Register Bits
BIT NAME DESCRIPTION
7 RS_P_N
The RS_P_N bit is only used when the I
2
C interface is in Master mode and
the ACK signal is not set to ‘0’ by the Slave with which it is communicating.
In this case:
0 = An I
2
C STOP condition is generated after each bus transaction.
1 = No STOP condition is generated.
6 R_W_N_CTRL
Read/Write Control The R_W_N_CTRL bit is only used when the I
2
C
interface is in Master mode. It sets the direction for data transfers:
0 = Write (Master transmitter)
1 = Read (Master receiver)
5P_TRNSFR
The P_TRNSFR bit is only used when the I
2
C interface is in Master mode.
When ‘1’, the I
2
C interface will terminate the data transfer after the current
I
2
C transaction has completed. Hardware will reset the P_TRNSFR bit to
‘0’ automatically.
4S_TRNSFR
Start Transfer When the I
2
C interface is in Master mode, a transfer, set-
ting the S_TRNSFR bit to ‘1’ will start a transaction on the I
2
C bus. When
the I
2
C interface is in Slave mode, setting the S_TRNSFR bit will transmit
a byte of data to the Master. Hardware will reset the S_TRNSFR bit to ‘0’
after the transaction.
3 FS_STD_N
Fast/Standard Speed
1 = Fast interface speed (400 kbit/s)
0 = Standard interface speed (100 kbit/s)
2I
2
C_EN
I
2
C Enable
1 = I
2
C interface is enabled
0 = I
2
C interface is disabled (SCL and SDA will not be driven)
1MODE[1]
I
2
C Mode
1 = Master mode
0 = Slave mode
0MODE[0]
I
2
C Mode
1 = 10-bit addressing
0 = 7-bit addressing