User`s guide

LZ87010 Advance User’s Guide I
2
C Interface
1/15/03 15-3
15.2.1 Slave Mode
In slave-receiver mode, the interface interrupts the processor whenever an address or
data byte has been received. The sequence is that the byte is received and acknowledged
by the interface, then the processor is interrupted. The ICDATA register will contain a data
byte, 7-bit Slave address, or one of the two 10-bit Slave address bytes. Status bits in the
ICSTAT and ICDBUG registers allow the processor to determine the type of transfer.
Whenever data is received, the ICSTAT.FULL_FLG bit is set. No further transfers can take
place over the interface until this bit is cleared. Reading the ICDATA register clears the bit.
In slave-transmitter mode, the interface interrupts the processor when an address is
received, when the interface is ready to receive another data byte, and on repeat START
conditions. When the interface is ready to send another byte, it sets the
ICSTAT.FULL_FLG bit. This will be cleared when the ICDATA register is written by the
processor. In slave-transmitter mode, the ICCON register must be written for each byte,
setting the ICCON.S_TRNSFR bit to initiate the transfer.
Interrupts set the ICSTAT.INT bit. Before the interrupt routine is exited, this bit must be
cleared by reading the ICSTAT register.
In address and repeat START transactions, reading the ICDATA and ICSTAT registers
is all that is required of the interrupt handler, since address comparisons are performed
in hardware.
15.2.2 Master Mode
Master mode is similar to Slave mode from an interrupt-handling point of view, but the
interface now transmits rather than receives addresses, and bus arbitration must be per-
formed as well.
Master-mode transactions start by testing ICSTAT.IDLE bit to verify that the interface is
idle, then initiating an address transaction. Address bytes and START bytes are generated
in software and written to the ICDATA register as if they were data.
The handling of individual data interrupts is much the same as in Slave mode.
15.3 Signals
Table 15-3. I
2
C Registers
SIGNAL
NAME
SIGNAL
TYPE
PIN
NUMBER
PIN
TYPE
FUNCTIONAL UNIT
SHARED
WITH
DESCRIPTION
SCL I/O 68 I/O I
2
CP3[6]I
2
C Bus Clock (Open Collector)
SDA I/O 69 I/O I
2
CP3[7]I
2
C Bus Data (Open Collector)