User`s guide

1/15/03 13-1
Chapter 13
Analog Inputs (ADC)
13.1 Theory of Operation
The 8 analog inputs AN[7:0] connect to an 8:1 analog multiplexer, which in turn connects
to a 12-bit analog-to-digital converter (ADC), using a successive approximation register
(SAR) algorithm. Figure 13-1 shows a block diagram of the ADC. The maximum voltage
of the ADC is set by the voltage reference signal ADVREF. The maximum conversion rate
is 500,000 samples per second (with a 10 MHz ADC clock). The ADC unit is clocked by a
divided HFCLK signal. The CLKCFG.ADCDIV field (described in Chapter 2) sets the
divisor. The ADC unit should be clocked between 1.6 MHz and 10 MHz.
The value returned by the ADC is formatted as a 16-bit unsigned integer with zeroes in the
least-significant 4 bits. The upper 8 bits are returned in ADCDH and the lower 4 bits are
returned in ADCDL. This value represents a fraction, where:
ADCD[H:L] = V(AN[ADCC.SEL])/V(ADVREF)
A value of 0xFFF0 (the maximum value) indicates that the analog input is greater
than (0xFFF0/0x10000) × ADVREF, or (4,095/4,096) × ADVREF. All voltages are
referenced to VSSA.
Using the ADC requires the following steps:
1. Set the ADC clock divisor to achieve an ADC clock rate between 1.6 and 10 MHz. This
uses the CLKCFG.ADCCLK field. For example, a value of 0b100 selects a clock
divisor of 4, suitable for a 40 MHz HFCLK oscillator.
2. Enable the ADC by setting ADCC.PWEN = 0b1. Wait for the ADC to power up (see
the ADC AC Specifications).
3. Select the desired ADC input pin (one of AN[7:0]) by writing the ADCC.SEL field with
a value equal to the signal number. For example, select AN[3] by setting
ADCC.SEL = 0b011.
4. Before each conversion, set ADCC.START to 0b1 to begin sampling (tracking) the
selected signal. The ADCC.STATUS bit will change to 0b0 to indicate that a start-of-
conversion request is now pending. The output of the previous conversion will remain
in the ADCDH and ADCDL registers until Step 6.
5. Wait at least one ADCCLK period to allow the inputs to settle after MUX selection.
6. Start the conversion by setting ADCC.START to 0b0. This will capture (hold) the
analog sample and process the A-to-D conversion.
7. Wait for conversion to complete. If the ADC interrupt is enabled, the interrupt handler
will be called upon completion. If polling, completion is indicated by
ADCC.STATUS = 0b1. (Note that ADCC.STATUS will be cleared on entry to the
interrupt handler, so this bit should only be tested in a polled environment.)
Conversion takes 16 ADCCLK cycles.
8. Read the resulting 12-bit unsigned ADC value from ADCDH and ADCDL.