User`s guide

Interrupts LZ87010 Advance User’s Guide
12-8 1/15/03
12.3.2 IE (Interrupt Enable) Register
The IE (interrupt enable) register contains a global interrupt enable bit and individual inter-
rupt enable bits for the standard 8051 interrupts.
Table 12-7. IE Register
BIT 7 6 5 4 3 2 1 0
FIELD EA /// /// ES ET1 EX1 ET0 EX0
RESET 0 0 0 0 0 000
RW RW RO RO RW RW RW RW RW
ADDR 0xA8
Table 12-8. IE Register Bits
BIT NAME DESCRIPTION
7EA
Enable All Global interrupt enable bit. If ‘1’, interrupt processing is enabled. If ‘0’,
all interrupts are disabled.
6:5 /// Reserved Reads return 0; write as 0.
4ES
Enable Serial Port 0 Interrupts If ‘1’, UART 0 interrupts are enabled. If ‘0’, they
are disabled.
3ET1Enable Timer 1 Interrupt If ‘1’, Timer 1 interrupts are enabled. If ‘0’, they are disabled.
2EX1
Enable External Interrupt 1 If ‘1’, INT[1] interrupts are enabled. If ‘0’, they
are disabled.
1ET0Enable Timer 0 Interrupt If ‘1’, Timer 0 interrupts are enabled. If ‘0’, they are disabled.
0EX0
Enable External Interrupt 0 If ‘1’, INT[0] interrupts are enabled. If ‘0’, they
are disabled.