User`s guide

Interrupts LZ87010 Advance User’s Guide
12-6 1/15/03
12.1.5.2 INT[7:2]
The external interrupts INT[7:2] consist of six interrupt pins sharing a single vector. The six
pins are either all level-triggered on a LOW level or all edge-triggered on a rising edge. See
Figure 12-1.
The INT[7:2] pins have no status register. Instead, these interrupts are mapped to the
same pins as P0[7:2]. Because both functions of dual-function pins are simultaneously
active, the state of the interrupt pins can be read by reading P0. P0[7] gives the state of
INT[7], for example.
This works well with level-triggered interrupts, but when INT[7:2] are used as edge-triggered
interrupts, a strobed interrupt assertion is likely to have been deasserted before the interrupt
handler can test P0, making it impossible to determine which interrupt pin was asserted. This
problem does not occur if only one of the INT[7:2] interrupt pins is used, or if the interrupt
strobe is held in the same manner as level-triggered level-triggered interrupts.
Figure 12-1. External Interrupts INT[7:2]
LZ87010-88
INT[7]
CLR
f(x)
X
ALTFEN1.IT2
ALTFEN1.IE2 CLR
INT[6]
INT[5]
INT[4]
INT3]
INT[2]
INTERNAL TO
THE LZ87010
EXTERNAL TO
THE LZ87010
IE1.EX2
TO
INTERRUPT
CONTROLLER
NOTE:
f(x):
If x = 0: Asserted if AND (INT[7:2]) = 0 (any signal LOW).
If x = 1: Strobed on transition from AND (INT [7:2]) = 1 to AND (INT [7:2]) = 0.
INTERRUPT
ACKNOWLEDGE