User`s guide

Interrupts LZ87010 Advance User’s Guide
12-4 1/15/03
12.1.3 Interrupt Sources
Most of the functional units in the LZ87010 can assert interrupts. The different interrupt
sources are listed in Table 12-3.
NOTE: *These status registers are cleared automatically upon entry to the interrupt handler, which means that the interrupt rou-
tine cannot test them successfully.
Table 12-3. Interrupt Summary
INTR. PIN ENABLE STATUS DESCRIPTION
ADC IE1.EADC ADCC.STATUS* ADC Interrupt Asserted at end of analog conversion.
DAC0 IE1.EDAC0 DAC 0, DAC 1 Interrupts Asserted after a pre-selected
number of waveform generator outputs, as set in
WGCFG(x).IVL[2:0]
DAC1 IE1.EDAC1
I
2
C SDATA IE1.EI2C ICSTAT.INTR I
2
C Interrupt Asserted when any I
2
C interrupt occurs.
INT[0] INT[0] IE.EX0 TCON.IE0*
External Interrupt 0 Asserted on LOW level if TCON.IT0 = 0;
asserted on falling edge if TCON.IT0 = 1
INT[1] INT[1] IE.EX1 TCON.IE1*
External Interrupt 1 Asserted on LOW level if
TCON.IT1 = 0; asserted on falling edge if TCON.IT1 = 1
INT[7:2] INT[7:2] IE1.EX2 P0[7:2]
External Interrupts 7:2 Asserted on AND(INT[7:0]) = 0
(any signal LOW) when ALTFEN1.IT2 = 0. Asserted on
rising edge of OR(INT[7:0] = 1 (rising edge of any signal) if
ALTFEN.IT2 = 1. Status of individual pins can be read on
P0[7:2] (same pins as INT[7:2]) if interrupt source is still
asserted when P0 is read by the interrupt handler.
TIMER 0 IE.ET0 Timer 0 Interrupt Asserted when Timer 0 overflows.
TIMER 1 IE.ET1 Timer 1 Interrupt Asserted when Timer 1 overflows.
TIMER 2,
TIMER 3
CTCAP2A,
CTCAP2B,
CTCAP3A,
CTCAP3B
IE1.ET2T3,
T(x)CAP.IIE0,
T(x)CAP.IIE1,
T(x)CMP.IOE0,
T(x)CMP.IOE1,
T(x)CON.OVF_EN
T(x)STA.CAP0_ST,
T(x)STA.CAP1_ST,
T(x)STA.CMP0_ST,
T(x)STA.CMP1.ST,
T(x)STA.OVF_ST,
Timer 2 and Timer 3 Interrupts Asserted when any
enabled interrupt condition in either Timer 2 or Timer 3
occurs. Set status bits must be cleared in software. The four
CTCAP(x)(y) pins can be used as general-purpose edge-
triggered interrupts as well as external event timers.
TIMER 4,
TIMER 5
IE1.ET4T5,
T(x)CMP.IOE0,
T(x)CMP.IOE1,
T(x)CON.OVF_EN
T(x)STA.CMP0_ST,
T(x)STA.CMP1.ST,
T(x)STA.OVF_ST,
Timer 4 and Timer 5 Interrupts Asserted when any
enabled interrupt condition in either Timer 4 or Timer 5
occurs. The status bits must be cleared in software.
UART 0
RXD0,
TXD0
IE.ES
SCON.RI,
SCON.TI
UART 0 Interrupt Asserted when either the receive buffer
is full or the transmit buffer is empty. The SCON.RI bit must
be cleared in software for further receive interrupts to occur.
UART1
RXD1,
TXD1
IE1.ES1
SCON1.RI,
SCON1.TI
UART 1 Interrupt As UART 0.