Service manual
FO-IS125N
5 – 9
Pin Name Pin No. Pin I/O I/O Type Signal Description
Line Interface Signals
P_DIBn 14 I/O - SSD DIB Negative. Provides clock and power to the LSD,
and transfers data, control and status information between
the SSD and the external LSD through the DIB for con-
nection to the telephone line.
P_DIBp 15 I/O. - SSD DIB Positive. Provides clock and power to the LSD,
and transfers data, control and status information between
the SSD and the external LSD through the DIB for con-
nection to the telephone line
Handset Interface Signals
S_DIBn 20 I/O - Handset DIB Negative. Transfers data, control and status
information between the SSD and the external LSD for con-
nection to an optional handset.
S_DIBp 21 I/O - Handset DIB Positive. Transfers data, control and status
information between the SSD and the external LSD for con-
nection to an optional handset.
Diagnostic/Config
EYESYNC 24 O GPH Serial Eye Pattern Strobe. EYESYNC is a strobe for load-
ing the D/A converters on an external eye pattern circuit.
EYECLK 25 O GPH Serial Eye Pattern Clock. EYECLK is an output clock for
use by the serial-to-parallel converters on an external eye
pattern circuit.
EYEXY/
SWCFG2
23 I/O PLB03 Serial Eye Pattern X/Y Output/Software Config Bit 2.
EYEXY is a serial output containing two 11-bit diagnostic
words (EYEX and EYEY) for display on an oscilloscope X
axis (EYEX) and Y axis (EYEY), using an external eye pat-
tern circuit. EYEX is the first word clocked out; EYEY fol-
lows. Each word is 8-bits. EYEXY is clocked by the rising
edge of EYECLK. This serial digital data must be converted
to parallel digital form by a serial-to-parallel converter, and
then to analog form by two digital-to-analog (D/A) convert-
ers.
This pin can also be used as SWCFG2, a configuration
input. During reset, the pin is three-stated and the value on
this pin is stored in the SWCONFIG register. An external
pull-up or pull-down resistor of about 75 kΩ is recom-
mended to set the value.
XCLK/SWCFG1 26 I/O PLB03 X Clock/Software Config Bit 1. Output clock at 70.56
MHz. It can be turned off at any time by setting bit 1 of reg-
ister $2E.
During reset, this pin functions the same as SWCFG2.
YCLK/SWCFG0 27 I/O PLB03 Y Clock/Software Config Bit 0. Output clock at 28.224
MHz. It can be turned off at any time by setting bit 0 of reg-
ister $2E.
During reset, this pin functions the same as SWCFG2.
Power/GND Pins
VDD 5, 29 - - Supply Voltage for Digital Circuits. +1.2 V from internal
regulator. The VDD pins must be decoupled to VSS-VSSO.
VDDO 7, 17 - - Supply Voltage for I/O Circuits. Connect to +3.3 V.
VSS-VSSO 6, 16, 28 - - Ground for the Digital Circuits and I/O Circuits. Connect
to digital ground.
PADDLE 33 - - Paddle Ground. The PADDLE, a conductive surface
located on the bottom of the package, is connected inter-
nally to VSS-VSSO ground.
Note: All pins have neither internal pull-up or pull-down resistors.