Service manual

FO-4700U
FO-47UC
5 – 7
PIN I/O Name Function
1 IO2M RTCDT RTC data input/output
2 O2M RTCCK RTC data transfer clock
3 O2M RTCCE RTC chip select
4 O2M RTCIO RTC inout/output control
5 TO GAIN Output port
6 I MTSTART Input port
7 I LCINT Interrupt request signal from LC82103
8 O2M XLCCS Chip select signal to LC82103
9 O AO9 Reading/QM-coder LSI address output
10 O AO10 Reading/QM-coder LSI address output
11 – GND Ground
12 O AO11 Reading/QM-coder LSI address output
13 O AO12 Reading/QM-coder LSI address output
14 O2M XLCRD Read signal to LC82103
15 O2M XLCWR Write signal to LC82103
16 O AO0 Reading/QM-coder LSI address output
17 O AO1 Reading/QM-coder LSI address output
18 O AO2 Reading/QM-coder LSI address output
19 O AO3 Reading/QM-coder LSI address output
20 – VDD Power supply
21 – GND Ground
22 O AO4 Reading/QM-coder LSI address output
23 O AO5 Reading/QM-coder LSI address output
24 O AO6 Reading/QM-coder LSI address output
25 O AO7 Reading/QM-coder LSI address output
26 O AO8 Reading/QM-coder LSI address output
27 O CRNT Output port
28 – GND Ground
29 O TXB1 B-phase current control output 1
30 O TXB0 B-phase current control output 0
31 O TXA1 A-phase current control output 1
32 O TXA0 A-phase current control output 0
33 O TXPB B-phase current direction setting
34 O TXPA A-phase current direction setting
35 I A12 System address input
36 I A11 System address input
37 I A10 System address input
38 I A9 System address input
39 I A8 System address input
40 – GND Ground
41 ID QMPDRQ DMA request input (QM-coder)
42 O2M XQMPDAK DMA acknowledge output (QM-coder)
43 ID QMCDRQ DMA request input (QM-coder)
44 O2M XQMCDAK DMA acknowledge output (QM-coder)
45 O2M XQMRD Read signal to QM-coder
46 O2M XQMWR Write signal to QM-coder
47 O2M XQMCS Chip select signal to QM-coder
48 IO2M D15 System data input/output
49 IO2M D14 System data input/output
50 IO2M D13 System data input/output
LZ9FJ59 (IC17) Terminal list
PIN I/O Name Function
51 IO2M D12 System data input/output
52 IO2M D11 System data input/output
53 IO2M D10 System data input/output
54 I A7 System address input
55 I A6 System address input
56 I A5 System address input
57 I A4 System address input
58 I A3 System address input
59 I A2 System address input
60 IS SHCK Clock (19.6MHz) from CPU
61 – GND Ground
62 – VDD Power supply
63 I A1 System address input
64 I A0 System address input
65 IO2M D9 System data input/output
66 IO2M D8 System data input/output
67 IO2M D7 System data input/output
68 IO2M D6 System data input/output
69 IO2M D5 System data input/output
70 IO2M D4 System data input/output
71 IO2M D3 System data input/output
72 IO2M D2 System data input/output
73 IO2M D1 System data input/output
74 IO2M D0 System data input/output
75 – GND Ground
76 IS XRESET Reset signal
77 O2M XINT7 Interrrupt request signal to CPU
78 O2M XINT4 Interrrupt request signal to CPU
79 O2M XWAIT Wait request signal to CPU
80 I XRAS Input RAS signal from CPU
81 I A18 System address input
82 I A19 System address input
83 I A20 System address input
84 I A21 System address input
85 I XCS2 Chip select 2 signal input
86 I XCS6 Chip select 6 signal input
87 I XWRL System write (high-order byte) signal
88 I XWRH System write (low-order byte) signal
89 I XRD System read signal
90 I XDACK0 DMA acknowledge 0 input from CPU
91 O2M XDREQ0 DMA request 0 output to CPU
92 I XDACK1 DMA acknowledge 1 input from CPU
93 O2M XDREQ1 DMA request 1 output to CPU
94 O2M XGABCS Chip select (gate array B)
95 O2M XSRAMCS Chip select (SRAM)
96 O2M XPGMCS Chip select (ROM)
97 I XMDMINT Interrupt request signal from Modem
98 O2M XMDMCS Chip select (Modem)
99 O XMDMRST Modem reset output
100 – VDD Power supply