Service manual

SH7040 (IC12) Terminal function
Classification
Bus control
Symbol
CASH
CASL
Input/Output Name
Function
output
High-order column
DRAM column address strobe timing signal.
address strobe
It is output when access to high-order Bbits of data is made.
output Low order column
DRAM column address strobe timing signal.
address strobe
RDWR
AH
output
Dram reading/writing
DRAM writing strobe signal.
output Address hold
Address hold timing signal for the device which used
address/data multiplex bus.
Multifunction
timer pulse unit
WRHH(QFP-144)
output HHside writting
Indicates that bit 24 is written from bit 31 of external data.
WRHL(QFP-144)
output
HLside wtitting
Indicates that bit 15 is written from bit 23 of external data.
CASHH(QFP-144)
output HH side column
DRAM column address strobe timing signal.
address strobe
It is output when access to bit 24 from bit 31 of data is made.
CASHL(QFP-144)
output
HL side column
DRAM column address strobe timing signal.
address strobe
It is output when access to bit 18 from bit 23 of data is made.
TCLKA
Input MTU timer
MTU counter external clock input terminal.
TCLKB clock input
TCLKC
TCLKD
TIOCOA
TIOCOB
TIOCOC
TIOCOD
Input/output MTU input capture/
Channel 0 input capture inputloutput conveyer outpuVPWM
output conveyer
output terminal.
(channel 0)
TlOClA
TlOCl B
Input/output MTU input capture/
Channel 1 input capture input/output conveyer outpuVPWM
output conveyer output terminal.
(channel 1)
TIOCPA
TIOC2B
Input/output MTU input capture/
Channel 2 input capture input/output conveyer output/PWM
output conveyer
output terminal.
(channel 2)
TlOCl A
TlOCl B
Input/output MTU input capture/
Channel 3 input capture input/output conveyer output/PWM
output conveyer
output terminal.
(channel 3)
TIOCl A
TlOCl B
Input/output MTU input capture/
Channel 4 input capture input/output conveyer outpuVPWM
output conveyer
output terminal.
(channel 4)
Direct memorv access
DREQO
Input DMA transfer request
From-external DMA transfer request input terminal.
controller (DMAC)
DREQl
DRAKO
(channel 0,l)
output DREQ request reception
From-external DMA transfer request input sampling reception
DRAKl
) (channel 0,l) 1 is output.
Serial communication
DACKO
DACKl
TxDO
output
output
DMA transfer strobe
From-external DMA transfer request external I/O strobe
(channel 0,l)
is output.
Transmission data
SCI 0 and 1 transmission data output terminal.
interface (SCI) TxDl 1 (channel Oto 1) 1
A.D converter
RxDO
Input
Reception data
SCI 0 and 1 reception data input terminal.
RxDl
(channel 0 to 1)
SCKO
Input/output Serial clock
SCI 0 and 1 clock input/output terminal.
SCKl
(channel 0 to 1)
AVcc Input Analog power
Analog power Vcc potential is connected.
AVss Input Analog ground
Analog power Vss potential is connected.
AVref (QFP-144) Input
Analog reference power
Analog reference power inpUt tefRIi?Ial.
AN0 - AN7
Input Analog input
Analog signal input terminal.
ADTRG input
AID conversion
AID conversion state external trigger input.
trigger input
5-5