Service manual

XFCR-MVP (IC4) Terminal descriptions
Pin Name Pin No. I/O
Input
Type
Output
Type
Pin Description
(Active low signals have an "n" pin name ending.)
CPU Control Interface
MIRQn 135 I HU Modem interrupt, active low. (Hysteresis In, Internal Pullup.)
SYSCLK 133 I H System clock. (Hysteresis In.)
TSTCLK 130 O 3XC Test clock.
Bus Control Interface
A[23:0] [1:6][8:13]
[15:20][22:27]
O T 3XT Address bus (24-bit).
D[7:0] [136:139]
[141:144]
I/O T 3XT Data bus (8-bit).
RDn 128 O 3XTT Read strobe.
WRn 127 O 3XTT Write strobe.
ROMCSn 120 O 2XT ROM chip select.
CS1n 122 O 2XT I/O chip select.
CS0n 57 O 2XTT SRAM chip select. (Battery powered.)
MCSn 121 O 2XC Modem chip select.
SYNC 126 O 2XC Indicates CPU op code fetch cycle (active high).
REGDMA 124 O 3XC Indicates REGSEL cycle and DMA cycle.
WAITn 125 O 3XC Indicates current TSTCLK cycle is a wait state or a halt state.
RASn 113 O 3XTT DRAM row address select.
CAS[2:0]n [110:112] O 2XTT DRAM column address select.
DWRn 109 O 3XTT DRAM write.
Prime Power Reset Logic and Test
DEBUGn 129 I HU External non-maskable input (NMI).
RESETn 131 I/O HU 2XO XFC Reset.
TEST 58 I C Sets Test mode (battery powered).
Battery Power Control and Reset Logic
XIN 59 I OSC Crystal oscillator input pin.
XOUT 60 O OSC Crystal oscillator output pin.
PWRDWNn 62 I H Indicates loss of prime power (results in NMI).
BATRSTn 61 I H Battery power reset input.
Scanner Interface
START 101 O 2XS Scanner shift gate control.
CLK1 100 O 2XS Scanner clock.
CLK1n 99 O 2XS Scanner clock-inverted.
CLK2 98 O 2XS Scanner reset gate control (or clock for CIS scanner).
VIDCTL[1:0] [97:96] O 2XC Control for video preprocessing circuits.
Printer Interface
PCLK/
DMAACK
29 O 3XC Thermal Print Head (TPH) clock, or external DMAACK.
PDAT 30 O 2XP Serial printing data (to TPH).
PLAT 31 O 3XP TPH data latch.
STRB[3:0] [33:36] O 1XP Strobe signals for the TPH.
STRBPOL/
DMARQ
37 I C Sets strobe polarity, active high/low or external DMAREQ.
UX-510U/UX-510C/UX-500U
UX-500C/FO-1460U
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