Service manual

39
DV-L70S
DV-L70BL
DV-L70W
1 VDD – Digitan power +3.3V
2 HADR (0) Input CPU Address bus
3 HADR (1) Input CPU Address bus
4 HADR (2) Input CPU Address bus
5 HADR (3) Input CPU Address bus
6 HADR (4) Input CPU Address bus
7 HADR (5) Input CPU Address bus
8 VSS – Digital GND
9 VDD – Digitan power +3.3V
10 HADR (6) Input CPU Address bus
11 HADR (7) Input CPU Address bus
12 HADAT (0) Input CPU Data bus
13 HADAT (1) Input CPU Data bus
14 HADAT (2) Input CPU Data bus
15 HADAT (3) Input CPU Data bus
16 VSS – Digital GND
17 VDD – Digitan power +3.3V
18 HADAT (4) Input CPU Data bus
19 HADAT (5) Input CPU Data bus
20 HADAT (6) Input CPU Data bus
21 HADAT (7) Input CPU Data bus
22 INT Input CPU Data bus
23 WAIT Input CPU Data bus
24 VSS – Digital GND
25 VDD – Digitan power +3.3V
26 HRD Input CPU read signal
27 HWR Input CPU write signal
28 HAS Input CPU address strobe signal
29 HCS Input CPU tip select signal
30 HIM Input CPU bus control selection signal (I/M mode = H/L)
31 MRST Input Reset signal
32 VSS – Digital GND
33 VDD – Digital power +3.3V
34 PXDO (0) Output Pixel data output
35 PXDO (1) Output
8-bit parallel video data conforming to ITU-R BT.601 and BT.656 standard (Cb/Y/Cr/Y)
36 PXDO (2) Output MSB=PXDO(7), LSB=PXDO(0)
37 PXDO (3) Output
38 PXDO (4) Output
39 PXDO (5) Output
40 VSS – Digital GND
41 VDD – Digital power +3.3V
42 PXDO (6) Output
43 PXDO (7) Output
44 PXCLKO Output Reference clock output for pixel data. 27 MHz
45 VSYNCO Output Vertical sync signal output
46 HSYNCO Output Horizontal sync signal output
47 VSYNCI Input Vertical sync signal output
48 VSS – Digital GND
49 VDD – Digital power +3.3V
50 HSYNCI Input Horizontal sync signal output
51 PXCLKI Input Reference clock output for pixel data. 27 MHz
52 PXDI (0) Input Pixel data output
53 PXDI (1) Input
8-bit parallel video data conforming to ITU-R BT.601 and BT.656 standard (Cb/Y/Cr/Y)
54 PXDI (2) Input MSB=PXDI(7), LSB=PXDI(0)
55 PXDI (3) Input
9-15. IC901 IX1516GE GAMMA S-P-TONE
Terminal
Terminal name In/Output Function