Specifications

PIN
No.
Pin name Signal name IN/OUT Destination Function
43 PARAD5 PARAD5 IN 74LCX245, USS-725 Parallel I/F data bus
44 GND GND IN GND
45 PARAD4 PARAD4 IN 74LCX245, USS-725 Parallel I/F data bus
46 PARAD3 PARAD3 IN 74LCX245, USS-725 Parallel I/F data bus
47 PARAD2 PARAD2 IN 74LCX245, USS-725 Parallel I/F data bus
48 V
DD
3.3V IN Power source
49 PARAD1 PARAD1 IN 74LCX245, USS-725 Parallel I/F data bus
50 PARAD0 PARAD0 IN 74LCX245, USS-725 Parallel I/F data bus
51 GND GND IN GND
52 GND GND IN GND
53 REV_1 REV_ OUT 74LCX245, I/F_CN Data direction control
54 SCAN_EN GND IN GND
55 SCAN_TEST GND IN GND
56 PDACK_1 PARACK_ IN ASIC(KZ4H167V06) DMA acknowledge signal from
ChipsetASIC
57 PDREQ_1 PARREQ_ OUT ASIC(KZ4H167V06) DMA request signal to ChipsetASIC
58 SCLK GA2CLK IN PLL IC (CY2292) Clock
59 DEVCS_1 1284CS_ IN ASIC(KZ4H167V06) OS_ signal to interface ASIC
60 DEVWR_1 PIAWE_ IN ASIC(KZ4H167V06) Write signal to interface ASIC
61 DEVRD_1 PIARD_ IN ASIC(KZ4H167V06), 74LVC16245 Read signal to interface ASIC
62 RES_1 RESET_ IN CPU Reset signal
63 VCCOK VCCOK IN ASIC(KZ4H167V06) V
CC
states effective
64 CPUD0 LDT0 IN/OUT 74LVC16245 Data bus
65 CPUD1 LDT1 IN/OUT 74LVC16245 Data bus
66 CPUD2 LDT2 IN/OUT 74LVC16245 Data bus
67 CPUD3 LDT3 IN/OUT 74LVC16245 Data bus
68 CPUD4 LDT4 IN/OUT 74LVC16245 Data bus
69 GND GND IN GND
70 CPUD5 LDT5 IN/OUT 74LVC16245 Data bus
71 CPUD6 LDT6 IN/OUT 74LVC16245 Data bus
72 V
DD
3.3V IN Power source
73 CPUD7 LDT7 IN/OUT 74LVC16245 Data bus
74 CPUD8 LDT8 IN/OUT 74LVC16245 Data bus
75 CPUD9 LDT9 IN/OUT 74LVC16245 Data bus
76 GND GND IN GND
77 CPUD10 LDT10 IN/OUT 74LVC16245 Data bus
78 CPUD11 LDT11 IN/OUT 74LVC16245 Data bus
79 CPUD12 LDT12 IN/OUT 74LVC16245 Data bus
80 V
DD
3.3V IN Power source
DM-1505
11 – 27