Service manual
3.
Description
of
each
block
3·1. LR38045
gate
array
Table
below
sh
ows
the
functions
and
port
add
ress
of
the
gate
array
block.
Block Function
B,
A bidirectional B·bit
input/output
buffer.
(S-bit
110
buffer)
M,
U58d
to
$ltleet FF1 . FF2, FF3,
or
PA
port
(multiplexer) when data are read from the gate arrav.
FF 1- FF3
FFI
:
The
interrupt circuit
is
controlled with
(S·bit latch)
an F
Fl
output.
For
in
stance, when a
cenain
bit
is
$Itt
to
" 1
",
th
e input
signal
to
the
PA
pon
(PAO-6tl
which
corresponds
to the bit
is
sent
on
the
I RQ line as an interru
pt
sig
n
al.
FF2:
PB
pon
(PBO-7N) l
atch
FF3
:
PC
port (PCO-7N) letch
DCI-3
DC1
:
For
generation
of
32KB R
OM
chip
(decoder)
sel
ect
signal. (CSNO)
OC2:
For
9I!neralion
of
2.5"
FDD select
signal.
(l07N)
DC3:
For
selection
of
FF1-FF3
and
FFD
reset latch
al
the time of data write.
Or selection of
FF1-
FF3
or
PA
pon
et
the
t ime of
data
relcl.
INT
Inputs
to
the
PA
port
(PAO-Bl ) are ORed
(interrupt circuit)
and
Sent on
the
IRQ line u an interrupt
signal.
As
PAD-61 correspond
to
00-06
of
FFI.
the interrupt
is
enabled when
FFI
is
set
with " 1
".
(Fig. 3 shows the quiva!ent circuit
of
the
interrupt circuit,)
'"
T
1b-
----=
.......,---
"
P,..,
0'
PAil
"
PAU
O. P
Ail
O.
PA"
"
PAOI
~
PA"
To multiplexer
(F
ig.
3) Interrupt circuit
RST
FFI
-3
are reset by this circuit, when a reset
(reset circuit)
sig
nal
is
received on RSTI.
At
th
e same time, t
he
2/5"
FOD reset signal
(RSTN)
is
issued which
will
be k8Pt active
until cleared by software.
-
65-
Block
Fu nction
-
PC
-
l600
It
is
possible
without
an
input
on
RSTIto
output
RSTN
by
means of software.
(
Fi
g.
4 sho
ws
the
equivalent circuit of the
reset circuit
and
Fig
. 5 shows its timings.)
._,_~
/{
,:
=C
,J
-
r-~~~
-;;
-
--
----,
~
'''
T
fW
i.
'T
:
""
ntli
0\$":
HI-lRUET
L
__________________
____
.;
(Fig.
4)
Reset circuit
(Fig.
5)
Reset circuit tImings
CMT IIF The cassette signal received from
the
EAR
(cusene
interface jack
is
amplified
and
waveform shaped.
circuit!
to
be
sent
on
PA7e.
(See Fig.6 f
or
its
equivalent circuit.}
P
_A
1"
_______
,
PAT
I ,
.,,"
r----'
,
I1JlJl
:
,
,
r;,
:
.
,
,
:
pn
.
L-.
:
~--------------------.
(Fi
g.
6)
Cassette interface circuit equivalent
circuit
NO
TE
:
Po
rts,
PA,
PB,
and
PC,
are
all
active
h
igh
within
the
gate
array,
but
they
are
converted
to
active
l
ow
signa
ls
outside
of
the
gate
array.
Gatll array
,
Inside' Outside
,
FF2
FFJ
ACTIVE HIGH
For
instance,
if
"1"
is
set
PBON
output
becomes
low.
PAD-61
PBON-7N
PCON-7N
ACTIVE L
OW
to
ao
of
FF
2,
the
I