Service manual
, .
I
I
-
PC
- l600
9-5. TC8576F
UART
pin d
esc
ription
The
TC8578P
Standard
Microcomputer
Interface (SMI)
is
a
si
ngle chip C·MOS L
SI
which
supports
the
R5-232C serial
interface
and
Centronics
compatible
parallel interface,
both
of
which are standard interfaces for
microcomputers
.
In
the
LSI
is
contained
the
RS-232C
ART
(Asynchronous
Receiver
Transmitter),
its
"'ud
rate
generator,
and
the
Centr
onics transm
itter
/rece
ive
r
interface.
Fo,
,h.
Con·
tronies interface,
either
tho
transmitte
r
or
,h.
receiver
mode
must
be
selected.
When
the
AR
T receives
data
fr
om
the
CP
U,
the
data
are
converted
into
serial form and
sent
out
on
the
TXO
line.
On
the
o
the
r hand, the serial
data
received
on
the RCO line
are conve
rt
ed i
nto
parallel
form
before being
handed
to
the
CPU. The
ART
is
able
to
inform
the
CPU
at
any
time
of
Pin
Symbol
In/Oul
Active
No.
level
1
INC)
-
-
Not
used.
the
completion
of
sending
the
data
received from the
CPU
or
the
reception of
the
data
to
be
handed
to
the
CPU
.
The clock in
put
of
the
Ie
is
divided
by
a 4-bi t program-
mabie prescaler
and
becomes
the
internal clock (SYS-CLK
),
wh
ic
h
is
further
divided by
the
baud rate generator com·
posed
of
a 12-bit
programmable
divider,
for
the
creatioo of
any
baud
rate
of
50
to 38,
400
bauds.
The
transmission/r
ecep
tion
handshake pins are provided for
the
Centron
i
cs
parallel interface. When
the
a-
bit
data
are
received from
the
CPU
in
the
transmit
mode, a strobe of
the
programmed pulse wi
dth
is
automat
ically issued. In the
receive
mode
, when
data
are received
with
a str
obe
singal
from
the external source, a busy singal
is
r
et
urned
to
auto-
mat
i cally inform
the
CPU.
Fu
nction
2
RD
In
L~
A
low
on this
li
ne
QUMS
the
CPU
to
read
data or
rt
..
us
infor
mat
ion
from
the
SMI.
3
WR
In
Low
A
low
on this l
ine
causes
the
SM
I to
receiv
e data or control
word
s
,e
nt
from
the
CPU
via
thl
date
bu
s.
4
es
In
Low
A
low
on this
lint!
causes
the
SM
Ito
be
activated.
Whln
B
is
at
I
high
IIVII,
both
RO
and
WR
a
rl
disabled.
AI
AO
RD
WR
~
Function
0 0 0
,
D
RXO-data
bus,
.I
rial
0 0
,
0 D
Data
bus
-
TXD,
serial
0
,
0 1 0
PIN _ data
bYs.
par,lIel
0 1
,
0 0 Data
bus
-
PVOUT,
parallel
,
0 0 1
0
Serial
statui
- data
bus
,
0
,
0 0
Data
bus
_ paraml
llr
regiltar
1 1 0
,
0 P
'r,
lIe
l
rtll1U
I-
dltl
bus
,
1 1
0 0
Data
bus
- command'" plramlter address
. . . .
,
Data
bus,
high
impedance
• don't
~"
. . , ,
0
Data
bus.
high
impedance
5,.
A1
,AD
In
-
11"1
combining th
is
signal
with
RD
or
WR,
the
CPU
selects the
contennol
the
dll1a
trlnsfer with the
SMI
.
1
GNO
Power
-
Po
wer
supply.
IUpply
8
INT
"u
H
igh
log
ical
OR
of four inte
rnal
signals
(RXRDY
,
TXRDY,
PRROY.
and
PTADY)
which
is
used
to
cause
an
interrupt to the
CPU.
9-16
07
-
00
In
/Out -
Dat
i bu$.
11
vee
p
~~
-
Power
supp
ly
.
supply
IS
GND
Po_
-
Power
supply.
SUpplV
-
32
-
~