Service manual
r
-
pc
:....
1600
47
GND
POWII'
supply.
48
A8
0"
Addr.u
bus
bee
Pin No.39).
49
VGG
POWBf
l
upplv
.
50-56
A9
- A15
D,,,
Addr
'"
bus (see Pin No.
39
1,
57
INC)
-
58
R
/W
0..,
Memory
write
signel. Wi
th
. low A
/W
stete
,
th
e
del
. in
the
CPU are sent
on
the
data
b UI .
59
p.
D,
,,
E
xt
ernal latch cl
ock.
With . high
"ete
of
th
is
clock,
thl
contents
of
th,
accu
mulato
r af.
tran
sferred
onto
the
data
bus. Use
of
the
In::h
Ie
permits
its
use as Ihe o
utput
pan
!see
the ATP eommand).
60
PV
0..,
TheM
.re
th
e CPU i
ntlrn
e'
flip-flop outtlUt pins IPU. PVI.
6'
PU
0.. ,
The ...
ert
commands to
Jet
and reset
PU
end
PV
.
"
.as
0..,
Ttle
clock,
in the
NIITlIl
ph, .
nth.
CPU inllrnel basic
clock,
is
on
thil
lin
e
to
supply
clock pulse to t he externel lystem,
When .
2.
6MHz
crys
tell
s
conntcted
&eross
XL.O
end XL 1, . 1.
3MHz
clock I. supplied.
63
XLO
,.
Cryn
al
connect
i
on
pin
..
X
LO
i.
en
input
and
X
l1
i.
11'1
outpUt.
64
XLI
0..,
Inlld e l
he
CPU,
the
clock
I.
divided
in
h'lf
, Whe
n.
2.6MHz crystal i. connec
ted
, the
mlChiM cycle within 1M
CPU
is
at
1.3MHz.
65
WAI
T
,.
CPU
wait signal. When th
is
Input
Is
high,
the
CPU'. Interna' operation clock
"11>"
S
lOpS
and tha
CP
U
th
areforeilop
i executing a
command.
When It
res
umes
II
l
ow
ltate,
the
CPU
lIarll
to
execute
a
command
.
I
nt
....
nal bas
ic
clock
.as
CPU
Op
....
ating clock
•
WAIT input
/
\
CPU internal
I
\
flip·
flopWA
NOTE:
WA
I.
th
e
CP
U
inllrn
el
flip·flOp for
WA
IT.
At.
high
to
low transition of ttle clock
4105, Input of
WAI
T
ilaccepted.
The
CPU
Operating clock
11>
ItOpS
wh
en
WA
lilt
h
lgh;!he
CPU
h ••
ts.
comm.nd
execution temporarilv as a result.
66
-73
IN7
-I
NO
,.
Input
PO".
The
CPU
c.
n send
the
signal
input
on
th. I
NQ-IN7
to
the
CPU
ICCUm
ulator
...
n
8-bit
data.
It
hH.n
Internal pull-up rHl
nor
. When
not
connected,
the
CPU
IIsum
"
the
line
to
be In high impedance.
74
-76
INC)
-
NOTE :
NC
: No
Connection
-
26
-
,"