Service manual

CD-DV999W/CD-DV777W
8 – 6
IC3401 RH-iX0614AWZZ: 64M S-DRAM (IX0614AW) (1/2)
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Pin No. Terminal Name Input/Output Function
1 VDD Input Power supply for internal circuits and the input buffer.
2 DQ0 Input/Output Multi data input/output pin.
3 VDDQ Input Power supply for the output buffer.
4, 5 DQ1, DQ2 Input/Output Multi data input/output pin.
6 VSSQ — GND.
7, 8 DQ3, DQ4 Input/Output Multi data input/output pin.
9 VDDQ Input Power supply for the output buffer.
10, 11 DQ5, DQ6 Input/Output Multi data input/output pin.
12 VSSQ — GND.
13 DQ7 Input/Output Multi data input/output pin.
14* N.C. — Not used.
15 VDD Input Power supply for internal circuits and the input buffer.
16 DQM0 Input/Output Controls output buffer during read mode and masks input data during write mode.
17 WE — RAS, CAS and WE define operations.
18 CAS — RAS, CAS and WE define operations.
19 RAS — RAS, CAS and WE define operations.
20 CS Input All inputs except for CLK, CKE and DQM are enabled or disabled.
21 N.C. — Not used.
22, 23 BA0, BA1 — The bank to be operated during RAS operation is selected.
The bank to read and write during CAS operation is selected.
24-27 A0-A2 — Line address: RA0-RA10; Column address: CA0-CA7
Auto precharge flag: A10
28 DQM2 Input/Output Controls output buffer during read mode and masks input data during write mode.
29 VDD Input Power supply for internal circuits and the input buffer.
30* N.C. — Not used.
31 DQ16 Input/Output Multi data input/output pin.
32 VSSQ — GND.
33, 34 DQ17, DQ18 Input/Output Multi data input/output pin.
35 VDDQ Input Power source for the output buffer.
36, 37 DQ19, DQ20 Input/Output Multi data input/output pin.
38 VSSQ — GND.
39, 40 DQ21, DQ22 Input/Output Multi data input/output pin.
41 VDDQ Input Power source for the output buffer.
42 DQ23 Input/Output Multi data input/output pin.
43 VDD Input Power supply for internal circuits and the input buffer.
44 VSS — GND.
45 DQ24 Input/Output Multi data input/output pin.
46 VSSQ — GND.
47, 48 DQ25, DQ26 Input/Output Multi data input/output pin.
49 VDDQ Input Power source for the output buffer.
50, 51 DQ27, DQ28 Input/Output Multi data input/output pin.
52 VSSQ — GND.
53, 54 DQ29, DQ30 Input/Output Multi data input/output pin.
55 VDDQ Input Power source for the output buffer.
56 DQ31 Input/Output Multi data input/output pin.
57* N.C. — Not used.
58 VSS — GND.
59 DQM3 Input/Output Controls output buffer during read mode and masks input data during write mode.
60-66 A3-A9 — Line address: RA0-RA10; Column address: CA0-CA7
Auto precharge flag: A10
67 CKE Input Controls internal clock signal. When the terminal is not operated, SDRAM is in either mode of
Power Down, Suspend, or Self-refresh.
68 CLK Input System clock input. All other input is registered in SDRAM of CLK rise.
69*, 70* N.C. — Not used.
71 DQM1 Input/Output Controls the output buffer during read mode and masks input data during write mode.
72 VSS — GND.
73* N.C. — Not used.
74 DQ8 Input/Output Multi data input/output pin.
75 VDDQ Input Power source for the output buffer.
76, 77 DQ9, DQ10 Input/Output Multi data input/output pin.
78 VSSQ — GND.
79, 80 DQ11, DQ12 Input/Output Multi data input/output pin.