User`s guide

A-12 Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide
CPLD Code
LCD_SPR = 1 ;
LCD_SPL := ENAB1 & !ENAB2 ;
"Note that the total number of lines must be an odd number
"so that the phase of REV alternates frame to frame.
REV := REV $ (HORZ == 1) ;
"
"End of LCD test code
"
"Other
"---------------------------------
!MBREQ_CF_DET = (!CF_CD1n & !CF_CD2n) ;
CF_ENAB = NEP_PRESn & GFX_PRESn ;
SA_PWR_ENn = !SA_PWR_EN ;
"---------------------------------
"IRdA receive is routed through CPLD to allow the TV_IR_EN signal to
"enable stripping the 38KHz carrier from a TV remote signal. As of 11/24/99 this
"function is not available. The CPLD is programmed to pass the IRXD_2 signal
"to the SA_RXD_2 pin on the SA1110.
SA_RXD_2 = IRXD_2 ;
"---------------------------------
"TVclk generator is a clock doubler that uses two flip flop chains that are clocked
"on opposite phases of the input clock. The last flop in each chain clears the
first flop.
"The pulse widths are a function of clock to out and clear to out times of the flops
"and the number of flops in the chain. The ADV7171 clock spec requires a min of an
8ns
"wide clock pulse which this circuit provides. The pulse width can be increased by
adding
"inverters/bufferes between the Q and AR signals. Another method is to add a second
stage
"of flipflops that are clocked by the first set. However the pz3128 has very
limited
"async cock resources and this scheme does not work with this CPLD.
X1 := 1 ;
X2 := 1 ;
TV_CLK = X1 # X2 ;
UART3_CLK = SYS_CLK ;
"Add logic to tristate outputs for in circuit test. Use an impossible input
"combination to enable tri-state.
"
"Preliminary