User`s guide

Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide A-5
CPLD Code
!VX_CF_OEn = !CF_ENAB # (CF_ON) ;
!VX_A3_0_OEn = (!CF_ENAB & !MBGNT_CF_IRQ) # (CF_ON) ;
"Add logic to tristate outputs for in circuit test. Use an impossible input
"combination to enable tri-state. SWAP_FLASH and CF_ENAB should not be true at the
"same time in a non-tester enviorment
"NO_TEST = !(SWAP_FLASH & CF_ENAB) ;
NO_TEST = 1 ;
"Preliminary
"Preliminary
"Preliminary
"Preliminary
end Asscntlp2;
A.2 LCD_P2.PHD File Contents
Here are the contents of the lcd_p2.phd file:
module LCD_P2
title ’LCD control chip for SA1110’
"
"
" Copyright © 1999 Intel Corp.
"
"Preliminary
"Preliminary
"Preliminary
"Preliminary
"
"11/24/99
"
"Pass 2 etch
"
"Revision history
"11/24/99 preliminary release for pass 2 etch
"
"Preliminary
"
"Version with clock shimming for 147MHz CPU and 44.1KHz sample rate
"this version takes the 74MHz SDRAM clock from SDCLK_2 and divides
"it by 6.5 using the fractional divide logic to produce a 11.34276923MHz
"256Fs clock which is 0.47% accurate.
"
"
"Preliminary
"Preliminary
"Preliminary