User`s guide

A-4 Intel

StrongARM

SA-1110 Microprocessor Development Board

User’s Guide

CPLD Code

"and will go true (1) after the BCR is written

BCR_OK := 1 ;

MBGNT_CF_IRQ = CF_IRQ_LVL2OE & CF_ON & BCR_OK ;

!CF_IRQ_LVL2OE = !FL_BNK1_CSn ;

!BSR_RDn = RD_nWR & !CS2n & (SA_A25 # CF_ENAB);

!BCR_WRn = !RD_nWR & !CS2n & (SA_A25 # CF_ENAB) ;

"CF_ON is an internal node to simplify the CF enable logic

CF_ON = CF_ENAB & !CF_BUS_ONn & BCR_OK ;

"Turn on BCR after first write

!BCR_OEn = BCR_OK ;

!NEP_REG_CSn = !CS2n & !SA_A25 & !CF_ENAB ;

!FL_BNK1_CSn = (!CS1n & !SWAP_FLASH) # (!CS0n & SWAP_FLASH) ;

!FL_BNK0_CSn = (!CS0n & !SWAP_FLASH) # (!CS1n & SWAP_FLASH) ;

"The pipe delay programmed into the bank 2 SDRAM must be matched by an equal

"delay in the XCV_DIR. Add or remove SDCS_BNK2_DIR stages as required.

SDCS_BNK2_DIR_1 := (!RAS_SDCS_2n & !SD_CASn & RD_nWR) ;

SDCS_BNK2_DIR_2 := SDCS_BNK2_DIR_1 ;

SDCS_BNK2_DIR_3 := SDCS_BNK2_DIR_2 ;

"XCV_DIR low is B to A, CPU read from daughter boards

"XCV_DIR high is A to B, deault and write

"When the SA1111 board is attached, the default drives SA1110 data out to the Xbus

"so that SA1110 reads from SDRAM and

"Flash can be seen by logic analyzers. Only when data is read from an Xbus

"device or the CF slot on the SA1110 board are the data transceivers

"turned to drive data from Xbus to SA1110.

!XCV_DIR = (!CS5n & RD_nWR) # (!CS4n & RD_nWR) # (!CS3n & RD_nWR)

# (!CS2n & !SA_A25 & RD_nWR)

# (!CS1n & !SWAP_FLASH & RD_nWR) # (!CS0n & SWAP_FLASH & RD_nWR)

# (!SA_PCE1n # !SA_PCE2n) & RD_nWR

# (MBGNT_CF_IRQ & !CF_ENAB & VX_OEn)

# (SDCS_BNK2_DIR_1 # SDCS_BNK2_DIR_2 # SDCS_BNK2_DIR_3) ;

!XCV_DATA_OEn= ((!SA_PCE1n # !SA_PCE2n) & CF_ON) # (!CF_ENAB) ;

"MBGNT_CF_IRQ is pulled down so that at after reset it is un-asserted. This

prevents

"the address transceivers from driving the SA1110 bus after power up reset.

ADR_DIR = MBGNT_CF_IRQ & !CF_ENAB ;