User`s guide

Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide A-3
CPLD Code
SDCS_BNK2_DIR_1 node ;
SDCS_BNK2_DIR_2 node ;
SDCS_BNK2_DIR_3 node ;
NO_TEST node ; "Node for tri-state enable used in tester
MBGNT_CF_IRQ pin 2;
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"Clock OE and reset equations
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Equations
"BCR_OK is clocked true (1) at the end of the first write to the BCR
BCR_OK.CLK = !BCR_WRn ;
SDCS_BNK2_DIR_1.CLK = SDCLK2 ;
SDCS_BNK2_DIR_2.CLK = SDCLK2 ;
SDCS_BNK2_DIR_3.CLK = SDCLK2 ;
SDCS_BNK2_DIR_1.AR = RAS_SDCS_2n ;
SDCS_BNK2_DIR_2.AR = RAS_SDCS_2n ;
SDCS_BNK2_DIR_3.AR = RAS_SDCS_2n ;
MBGNT_CF_IRQ.OE = CF_ENAB & NO_TEST ;
CF_IRQ_LVL2OE.OE = !CF_ENAB & NO_TEST ;
ADR_DIR.OE = NO_TEST ;
XCV_DIR.OE = NO_TEST ;
"XCV_DATA_OEn.OE = NO_TEST ;
VX_CF_OEn.OE = NO_TEST ;
FL_BNK1_CSn.OE = NO_TEST ;
FL_BNK0_CSn.OE = NO_TEST ;
NEP_REG_CSn.OE = NO_TEST ;
BSR_RDn.OE = NO_TEST ;
BCR_WRn.OE = NO_TEST ;
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"Logic equations
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Equations
"BCR_OK will go false (0) when power is applied