User`s guide

4-30 Intel

StrongARM

SA-1110 Microprocessor Development Board

User’s Guide

Hardware Considerations

4.12.3 Stereo Codec Interface

The UDA1341 interfaces to the SA-1110 SSP port. The SSP must be configured in a TI

synchronous serial format with 16 bit data slots. A small amount of glue logic is required to

interface the UDA1341 to the SSP port. Figure 5-3 shows a simplified version of the glue. The

logic is implemented in the SA-1110 Development Board control CPLD.

Figure 5-4 shows how the glue logic modifies the SSP TI synchronous serial format to match the

I2S format used by the UDA1341. The UDA1341 must be configured using the L3 interface to

communicate in an MSB-Justified format with 16 bit data slots.

Figure 4-3. Stereo Codec Glue Logic

A7266-01

GPIO19 SSP

CLK IN

CODEC

256 FS SYSCLK

CODEC

Word

Select

CODEC BCLKGPIO12 SCLK

GPIO13 SSP

SFRM

11.98 MHz from

MCP Clock

CODEC RESET L

Divide

by 4

Figure 4-4. UDA1341 Interface Timing

A6949-01

SCLK

SFRM

Tx and

Rx Data

BCLK

MSB MSB-1 MSB-2