User`s guide

Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide 4-25
Hardware Considerations
4.11.2.2 Virtual Backup Battery
The linear boost bootstrap design relies on an LDO regulator in parallel with a boost converter and
a post LDO regulator to automatically load switch as the battery voltage falls from a high of 4.1 V
down to the 3.45 V main LDO drop out voltage. Below the 3.45 V main LDO drop out, the 3.3 V
circuits are powered by the 3.2 V LDO, which is powered from the boost regulator at the 5.5 V.
The linear boost bootstrap design is over 90% efficient for over 90% of the discharge cycle. The
design supplies full-system power all the way down to a 0.9 V battery voltage (well below the
2.7 V battery lockout point). However the full power 3.3 V efficiency is much less
(0.9 X 3.2/5.5 X 100= 52%) when the battery is below the 3.45 V point.
By reserving the bottom 10% of the charge as a virtual backup battery, the system can avoid the
reduced full-load conversion efficiency for the last 10% of the charge cycle and uses it instead to
eliminate the back up battery that is normally required. With the linear boost bootstrap circuits in
sleep mode, the last 10% of the charge is used at a 73% conversion efficiency. For example, if the
last 10% of the charge is at 100 mah and the 3.3 V sleep load is 1 ma, then the virtual battery lasts
73% of 100 mah or 73 hours, or about three days. If longer sleep times are required, the voltage
threshold where the virtual backup battery provides power can be raised.
The virtual battery design provides a direct read of the battery voltage through the UCB1300
Analog to Digital converters. The OS should notify the user to recharge or swap batteries as the
battery voltage approaches the 3.45 V virtual backup battery point. A low battery interrupt is also
provided as an alternative to scheduled battery voltage readings through the UCB1300. This low
battery interrupt is set at 3.5 V and is only active when the LCD is powered on. The low battery
interrupt results in the user receiving a two minute warning before an OS invoked sleep shutdown.
A hardware forced sleep mode is also provided with a MAX812 voltage sensing chip that drives
the SA-1110 VDD_FAULT signal when the battery drops below 3.08 V. The MAX812 may be
eliminated if the OS managed battery monitor and sleep mode entry is reliable and the OS never
hangs.
A very high value capacitor of 0.33 Farads (known as a supercap) connected in parallel with the
battery supports the system in sleep mode for several minutes if battery changes are required. A
low value resistor (1 ohm) in series with the supercap is essential to reduce inrush current when a
charged battery is attached to a discharged supercap.
The virtual backup battery circuit used in the SA-1111 Development Module is, of course, an
optional system design feature. Other designs may need real backup batteries as required by the
application.
4.11.2.3 Linear Boost Bootstrap System
Figure 5-2 shows the complete linear boost bootstrap system with virtual backup battery. Not
shown are the low-battery interrupt-sensing circuit and the end-of-charge forced-sleep-mode
circuit.