User`s guide

Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide 4-9
Hardware Considerations
2. Write 0xFF to GPIO 9:2
3. Configure GPIO 9:2 as inputs
4. Read GPIO 9:2 and save as system configuration byte.
High value resistors (100 K Ohms) are attached between GPIO 9:2 and ground on those bits that
must read as zeros in the configuration status register. High value resistors are required to minimize
wasted power in the resistors while the LCD is operating. These 100K ohm pull-down resistors
allow the GPIO pin to return to a valid zero level when the GPIO pins are configured as inputs.
To read the SCR bits, the boot code must first configure the GPIO 9:2 pins as outputs and then set
them to 0xFF very early in the boot process. This precharges the GPIO 9:2 pins to 3 volts. The boot
code must then configure the GPIO 9:2 pins as inputs and read the pins. The boot code must then
store the configuration information in a global area so that drivers and system services can
subsequently utilize the information.
The pins that have the 100K ohm pull-down resistors settle to a valid zero level in less then 2
microseconds. The pins that do not have pull-down resistors maintain valid high levels for more
then 10 microseconds. Due to these time constraints, the SCR boot code needs to sample the GPIO
9:2 pins only during valid times.
A section of boot code that allows the SCR bits to be read at a valid time is shown in Example 4-1:
Example 4-1. Boot Code to Read SCR Bits
ldr r0, =GPDR_PHYSICAL ; equate with physical address of GPIO
; pin direction register
ldr r1, =0x0807A7FC ; SA1110DB Pin direction, for now get rid of
; MBGRNT, STEREO, RXD
str r1, [r0]
ldr r0, =GPSR_PHYSICAL ; to find out SA-1110 HH board config must
; write FF
; to GPIO 2:9
ldr r1, =GPIO_2_T0_9 ; writing 0 has no effect so can blast the 1s in
str r1, [r0]
ldr r0, =GPDR_PHYSICAL ; now configure pins 2 through 9 as input
ldr r1, =0x0807A400
str r1, [r0]
ldr r0, =GPLR_PHYSICAL ; equate with physical address of GPIO pin level
; register
mov r2,#0x64 ; 100 decimal
10
ldr r1, [r0] ; now read pins to determine the configuration
subs r2,r2,#1 ; loop 100x through to make sure the pin bleed
; down takes
bne %b10
and r1, r1, #GPIO_2_T0_9; mask off non-configuration pins
ldr r0, =CONFIG_PHYSICAL; equate with address of area to store
; SCR configuration info for later use
str r1, [r0] ; store configuration in global area
ldr r0, =GPDR_PHYSICAL
ldr r1, =0x0807A7FC ; restore correct pin direction
str r1, [r0]