User`s guide

4-8 Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide
Hardware Considerations
4.4 Register Descriptions
This section describes the following registers:
• System configuration register—to control SDRAM size, flash size, and type of module such as
SA-1111 development module.
• Board configuration register—to control the compact flash, codec, IRDA, stereo, audio, LCD,
RS232, LEDs, communication ports, charger, radio, and speaker.
• Board status register—to control communications and radio ports.
4.4.1 Intel
®
StrongARM
®
SA-1110 System Configuration Register
SCR
The SA-1110 Development Board supports several different SDRAM and flash memory types and
sizes as well as different LCD types and multiple daughter cards. To allow the system boot code to
correctly configure the SA-1110 memory interface and timing registers, the SA-1110 Development
Board uses GPIO 9:2 pins to input system configuration information at boot time.
Note: In this document, the System Configuration Register (SCR) is referred to as a register, though no
register actually exists and therefore there is no corresponding address. The register bits are
composed of GPIO pins with some of them connected to pull-down resistors.
In the SA-1110 Development Platform, the GPIO 9:2 pins serve two functions: first as SCR bits
that can be read at boot time, and later as the upper 8 bits of the LCD data port.
After system reset and boot, all SA-1110 GPIO pins are reset to be inputs. During the boot
sequence the boot code performs the following sequence to determine the system configuration:
1. Configure GPIO 9:2 as outputs
GP[22]
MBREQ
CF_
CardDetect
MBREQ SA-1110 DMA bus request signal when the SA-1111 Development Module is
attached
CF compact flash card detect interrupt when no daughter boards are attached
CF_CD1 and CF_CD2 are logically AND’ed on the SA-1110 Development Board
0 – CF card present
1 – CF card absent
GP[23]
UCB1300_
IRQ
UCB1300 Codec, UCB_GPIO and touch screen interrupts
GP[24]
GXF_IRQ
CF_BVD2
Graphics daughter board interrupt
CF_BVD2 signal when no daughter boards are attached
GP[25]
SA-1111_IRQ
CF_BVD1
SA-1111 Development Module interrupt
CF_BVD1 signal when no daughter boards are attached
GP[26]
VBATT_LOW
_IRQ
RClk
VBATT_LOW_IRQ Low battery interrupt
RClk, CPU coreclk/2 to clock logic analyzer pods when SA-1111 Development Module is
attached.
GP[27] 3.68M_32K 3.68 MHz SA-1111 and GFX PLL reference clock and GFX 32 KHz power up clock
GP[31:28] Reserved –
Table 4-4. GPIO Pin Descriptions (Sheet 2 of 2)
Pin Name Signal Name Description