User`s guide

Intel
®
StrongARM
®
SA-1110 Microprocessor Development Board User’s Guide 4-7
Hardware Considerations
4.3.2 Intel
®
StrongARM
®
SA-1110 GPIO Pin Descriptions
Details of the SA-1110 GPIO pins are shown in Table 5-4. Pin Name indicates the actual name of
the pin on the SA-1110 device, while Signal Name indicates the signal name and function on the
SA-1110 Development Module.
Table 4-4. GPIO Pin Descriptions (Sheet 1 of 2)
Pin Name Signal Name Description
GP[0] On_Off_Sw1
Main system software control on/off switch
Application dependent switch. Used to toggle main system power between run and sleep
modes.
GP[1]
On_Off_Sw2
and Spare
FIQ
Secondary system software control on/off switch
Application dependent switch. Used to toggle backlight power on and off. May function as
one touch record button that wakes up system to record audio.
Secondary function as a spare FIQ interrupt if required by GFX board.
GP[9:2]
LCD_D(15:8)
CNFG(7:0)
LCD data for upper 8 bits of 16 bit color
After system boot, these pins should be configured to drive the upper LCD data bits.
System configuration information
At system boot time, GPIO 9:2 may be read to determine system configuration. Refer to
CNFG table.
GP[13:10]
SSP_
UDA1341
SSP UDA1341 stereo codec port
GP[14] Radio_IRQ
Radio Interrupt request
0 – No interrupt
1 – Interrupt
Only available when radio board is attached.
GP[15]
L3_SMB_
SDA
Shared L3 and SMB control ports
SMB data
L3 data is part of the L3 control bus to the UDA1341 stereo codec.
The System Management Bus (SMBus) is used to control smart battery chips
GP[16]
PSMODE_
SYNC
Power supply mode and sync control
0 – Low power operation for sleep mode
1 – High power, low noise operation for run mode
Sync – Program SDLC clock out to synchronize power switches. Used to reduce RFI and
video or audio noise
GP[17]
L3_MODE
LED
L3 mode signal with LED
L3 MODE is part of the L3 control bus to the UDA1341 stereo codec.
This GPIO has a LED that may be used by the boot code to indicate boot status by
flashing codes. After boot time this GPIO must function as the UDA1341 MODE signal.
GP[18] L3_I2C_SCL
Shared L3 and I2C control ports
I2C clock
L3 clock is part of the L3 control bus to the UDA1341 stereo codec.
SCL is used as System Management Bus (SMBus) to control smart battery components
GP[19]
SSP_UDA
1341
Extrn_Clk
SSP UDA1341 stereo codec external clock input
Inputs 1.4976MHz 32Fs clock for 46.8KHz audio sample rate.
GP[20]
UART3 CLK/
SPARE
UART3 Clock input
User to provide high speed clock to UART3. UART3 is used as the radio communications
port. Bluetooth radio may require use of the external UART3 clock. Also a possible spare
GPIO if Bluetooth is not present.
GP[21]
MBGNT
CF_IRQ
MBGNT SA-1110 DMA bus grant signal when SA-1111 development is attached
CF_IRQ compact flash interrupt when no daughter boards are attached