Intel® StrongARM® SA-1110 Microprocessor Development Board User’s Guide ADVANCE INFORMATION January 2000 Hardware Build Phase 4 Notice: This document contains information on products in the sampling and initial production phases of development. Revised information will be published when this product is available.
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document.
Contents 1 Introduction ............................................................................................................. 1–1 1.1 1.2 2 Getting Started ........................................................................................................2–1 2.1 2.2 2.3 3 Physical Description.....................................................................................2–1 2.1.1 Unpacking the Intel® StrongARM® SA-1110 Development Board.2–5 2.1.2 Development JTAG.....................
.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 5 Analog I/O............................................................................................................... 5–1 5.1 5.2 5.3 6 UCB1300 Analog IO .................................................................................... 5–1 5.1.1 Battery Voltage ............................................................................... 5–1 5.1.2 Battery Temperature ....................................................................... 5–2 5.1.
6.2.5 6.2.6 6.2.7 A CPLD Code ............................................................................................................. A–1 A.1 A.2 B Battery Safety ................................................................................. 6–3 Fuel Gauging ..................................................................................6–4 Special Handling and Storage Requirements for Batteries.............6–5 ASSCNTL_P2.PHD File Contents .....................................................
Introduction 1 The Intel® StrongARM® SA-1110 Microprocessor (SA-1110) is a highly integrated communications microcontroller that incorporates a 32-bit StrongARM® RISC processor core, system support logic, multiple communication channels, an LCD controller, a memory and PCMCIA controller, and general-purpose I/O ports. For more information about the SA-1110 device, see the Intel®StrongARM® SA-1110 Microprocessor Developer’s Manual, order number 278240.
Introduction Figure 1-1. Preliminary Intel® StrongARM® SA-1110 Developer Platform 0.75" Intel® StrongARM® * SA-1110 hand held reference design. Add shield gnd points every 0.5" around entire board LCD CPLD LEDs Reg16 Sharp 3.9" color reflective TFT LCD Reg16 LCD GOO Light Green: 3V side one components Dark Green: 3V side two components Blue: 1.65V Vcore Red: 5V Yellow: LCD components Magenta: System power components cia L Hi 3V A3-A0 AA Batt. Li-ion UR 14500 Dxcv L 0.
Introduction Figure 1-2 shows a preliminary sideview of the SA-1110 development board: Figure 1-2. Preliminary Cross-Sectional view of SA-1110 Development Platform Touch Screen Front Light Sharp Reflective 3" LCD 2.25" Full development system with Intel® StrongARM®* SA-1111, GFX, LCD, touch screen and frontlight. GFX Speaker mic SA-1110 mic XCVR 0.775" SDRAM 32 Surface mount leds XCVR SA-1111 5" 5 cm Plexi Glass 1.5" 3.
Introduction 1.
Introduction • Phillips Semiconductor UCB1300* codec supports microphone, speaker, POTS line soft modem DAA connections and touch screen • Phillips Semiconductor UDA1341* stereo codec supports high quality 16 bit stereo audio record and playback • Infra-red interface for IrDA data links up to 4Mb • Battery powered, using high efficiency DC-DC converters and a single Lithium ion (Li-ion) cell • Smart battery technology development platform and reference design when used with smart battery packs • Integr
Introduction The graphics accelerator board has the following features1: • Third-party high performance graphics accelerator • Two head display support; Analog XGA and LCD XGA • Direct connection for Sharp LM8V31 dual scan STN VGA color panel with backlight and touch screen 1. 1-6 For more information about the graphics accelerator board, see the third-party documentation.
Getting Started 2 This SA-1110 Development Board is supplied as a mother board and functions as both a standalone handheld PC device as well as a development platform when used with the SA-1111 Development Module. This chapter provides a physical description of the SA-1110 Development Board and describes how to: • Unpack the card and give it a visual inspection • Verify SA-1110 Development Board kit contents • Install the required hardware 2.
Getting Started • 140-pin expansion header—Main connector for SA-1111 Development Module (daughter) or third-party daughter cards • Video out header—Five-pin connector that provides composite video The following components and systems are on side two of the SA-1110 Development Board: • Base station connector—14-pin connector for JTAG programming, RS232, power input jack, and telephone • • • • • • • • • GPIO 0 switch—Manual override for GPIO 0 GPIO 1 switch—Manual override for GPIO 1 User software defin
Getting Started Figure 2-1.
Getting Started Figure 2-2.
Getting Started Unpacking the Intel® StrongARM® SA-1110 Development Board 2.1.1 Warning: This board contains electronic components that are susceptible to permanent damage from electrostatic discharge (static electricity). To prevent electrostatic discharge, it is supplied in an antistatic bag.
Getting Started Caution: 2.2.1 If the 140-pin connector is damaged due to an improper assembly, the reader must contact their Intel Sales representative for module replacement.
Getting Started 3. Insert the power jack that is connected to the wall brick into J10 (see Figure 2-4 for the location of J10). J16 J7 J1 J11 J10 J5 J14 J17 Figure 2-4. AC Power Input Jack Location Base Station Power Input Jack Headset Jack 2.5 mm Stereo Jack 3.5 mm USB Type B Connection A7615-01 Note: The power jack may have to be rotated to its flat side to accommodate any other connectors in J10. 4. Plug in the wall-brick into an AC outlet. 5. See the Readme.
Getting Started Caution: Note: The following procedure assumes that the jumper (shunt) for J22, the Master Power Clip for the Li-ion battery, has been disconnected and that all power associated with the SA-1110 Development Board is off. For more information about Li-ion battery considerations, see Chapter 6. A very high value capacitor of 0.33 Farads (super cap) is connected in parallel with the battery through J22.
Getting Started 3. Insert the jumper (shunt) for J22 on the Master Power Clip (this jumper connects the two bare pins enabling the Li-ion battery.). Figure 2-7. Master Power Clip Location Master Power Clip Reset Switch J22 S9 Video Out Header J2 J18 (Momentary) LCD Cable Connector 140-pin Expansion Header for Intel® StrongARM® SA-1111 Development Module or other Daughter Card 4. See the Readme.txt file for success and failure indications of start-up diagnostic results and how to proceed.
Getting Started Figure 2-8. E11 Location on Side 1 J22 J8 E2 Large Dimple for Pin 1 Indicator Intel® StrongARM® * SA-1110 E1 J9 J2 J18 S9 J16 J7 J1 J11 J10 J5 J14 J17 J19 J21 E11 Intel® StrataFlash™ * StrongARM is a registered trademark of ARM Ltd.
Getting Started 3. Slide the middle top section of the box away from the notch in E11. Open the right hand side of the socket, then open the left hand side of the socket (see Figure 2-9). Figure 2-9. Opening the E11 Socket A7484-01 4. Using the Pen Vac tool, remove the low side (bits 0-15) StrataFlash memory component from the shipping container. 5. Insert the low side StrataFlash memory component into the socket aligning the pin 1 indicators. 6. Close up the socket. 7.
Getting Started . Figure 2-10.
Theory of Operation 3 The SA-1110 Development Platform is designed for the hardware and software development of hand-held, palm-top and tethered applications. The SA-1110 Development Platform provides all the system components necessary for a Windows* CE or other OS hand-held PC system or a subnotebook system development platform including three independent video heads, high-quality stereo sound and radio interface support. 3.
Theory of Operation Figure 3-1. Intel® StrongARM® SA-1110 Development Platform Block Diagram Intel® StrongARM®* SA-1110 CPU Board LCD Header LCD CPLD data LCD analog support formater for Sharp 3.9" for Sharp 3.
Theory of Operation As shown in Figure 3-2, the system partitioning allows the SA-1110 Development Board to be used by itself as a minimal palm-size PC system. All device interfacing is implemented with in-system programmable CPLDs and most system interface points are available on connectors suitable for daughter boards or cables. Figure 3-2.
Theory of Operation Although not intended as a ready to manufacture product design, the SA-1110 Development Board provides the basis for low-cost derivative designs. Figure 3-3 shows how data flows within the SA-1110 Development Module. Figure 3-3.
Hardware Considerations 4 This chapter provides an in-depth description on the following topics: • • • • • • • • 4.1 Xbus expansion headers Storage GPIOs Registers Displays Buses and Ports Power Audio Xbus Expansion Headers The general-purpose expansion bus headers provided on the SA-1110 Development Board are referred to as the Xbus headers (not to be confused with ISA Xbus). All SA-1110 address, data and memory interface signals are buffered before driving the Xbus headers.
Hardware Considerations Table 4-1.
Hardware Considerations 4.2.3 Main SDRAM Interface The SA-1110 Development Board provides support for 64 Mbit, 128 Mbit or 256 Mbit SDRAMs. The 54 pin TSOP footprint supports a wide variety of SDRAM vendors and densities. The system partitioning is designed to minimize the loading and etch length on the SA-1110 pin bus. This permits the system to run up to 103 MHz SDRAM using SA-1110 CoreClk/2 and 125 MHz SDRAM components. Using two 256 Mb 16 Mx16 SDRAMs provides a main memory load of 64 MBytes.
Hardware Considerations Development Module is not attached and the SA-1110 Development Board CF slot is active then GPIO 21 and GPIO 22 are used as CF RDY interrupt signals and CF card detect interrupt while GPIO 24 ad GPIO 24 are used as CF BVD2 and CF BVD1 inputs. Note: The SA-1110 Development Board CF slot is addressed in the same address space as the SA-1111 Development Module’s CF and PCMCIA slots, however the CF slot control signals and interrupt signals are not the same.
Hardware Considerations Note: GPIO 0 and GPIO 1 are the only wake up events that can cause the SA-1110 to come out of sleep mode if sleep mode was entered as a result of VDD_FAULT or BATT_FAULT signals. Table 4-2. GPIO Usage for Intel® StrongARM® Platforms GPIO a. b. SA-1100 Development Platforma SA-1100 Multimedia and SA-1101 Development Boards b SA-1110 Development Platform 27 32 KHz Out 3.68 MHz Out 3.
Hardware Considerations Table 4-3. UCB 1300 CODEC GPIO a. b.
Hardware Considerations Intel® StrongARM® SA-1110 GPIO Pin Descriptions 4.3.2 Details of the SA-1110 GPIO pins are shown in Table 5-4. Pin Name indicates the actual name of the pin on the SA-1110 device, while Signal Name indicates the signal name and function on the SA-1110 Development Module. Table 4-4. GPIO Pin Descriptions (Sheet 1 of 2) Pin Name Signal Name Description Main system software control on/off switch GP[0] On_Off_Sw1 GP[1] On_Off_Sw2 and Spare FIQ Application dependent switch.
Hardware Considerations Table 4-4.
Hardware Considerations 2. Write 0xFF to GPIO 9:2 3. Configure GPIO 9:2 as inputs 4. Read GPIO 9:2 and save as system configuration byte. High value resistors (100 K Ohms) are attached between GPIO 9:2 and ground on those bits that must read as zeros in the configuration status register. High value resistors are required to minimize wasted power in the resistors while the LCD is operating.
Hardware Considerations Table 4-5 provides bit descriptions of the SCR: Table 4-5.
Hardware Considerations Note: The BCR is not reset at power up time and is maintained during sleep mode. System software must initialize this register very early in the cold power up code. Table 4-6.
Hardware Considerations Table 4-6.
Hardware Considerations Table 4-6.
Hardware Considerations Table 4-6.
Hardware Considerations Note: The BSR is updated after each read to the BSR—to capture the present value of the BSR, two consecutive read operations are required. Table 4-7. 32-Bit Register Table 3 0 2 9 2 8 2 7 2 6 2 5 2 4 Rad_RI Rad_DSR Rad_CTS COM_DSR COM_CTS COM_DCD RS232_Valid Reset X X X X X X X X Bit a.
Hardware Considerations 4.6.1 LED Displays There are six LEDs on the SA-1110 Development Board. These are primarily intended to provide general status and power status and some low-level system debug and development support. Many more system debug LEDs are on the SA-1111 Development Module. Table 4-8. LED Descriptions LED Name Description GPIO 17 LED D13 GPIO 17_LED D9 D9_LED D8 D8_LED Used to signal boot diagnostic status. General purpose boot progress indicator.
Hardware Considerations mappings between the SA-1110 and the LCD that the CPLD can be programmed to accommodate. In addition, no two LCDs are the same and the CPLD allows developers to adapt designs to support other displays types or NTSC/PAL TV encoders. This LCD CPLD facilitates the adaptation of many different LCD types to the SA-1110 Development Board. The SA-1110 Development Board provides all required support circuitry for the 3.
Hardware Considerations 4.7.2 Debug Switches A switch pack containing eight switches is provided on the SA-1111 Development Module. The switches may be read in the SWPK register. With the exception of Switch 8, which controls the boot ROM bank select, the switch definitions are “soft” and may be defined by the debug environment. 4.7.3 Function Switches The SA-1110 Development Board has eight switches. These switches are mounted on the side of the board and may be activated while booting the device.
Hardware Considerations 4.8 SMBus The SMBus interface is a two-wire serial protocol requiring open-collector drivers that allow the “wire or” of data on the SMBus. The SMBus SDA (data) and SCL (clock) have pull-up resistors to VDD such that an un-driven SMBus pin will be high (one). The GPIO pins on the SA-1110 Development Module are three-state drivers that have programmable control of direction and data as well as interrupt generation from either or both edges of a signal.
Hardware Considerations Note: 4.10 The nine-pin RS232 cable connected to the Base Station serial port (J10) on the SA-1110 Development Board cannot be connected at the same time as the UART1 connector on the SA-1111 Development Module. Failure to do so will corrupt the data on the UART1. Power System The SA-1110 development system has a unique, highly efficient and cost effective battery power system. 4.10.
Hardware Considerations cells result in a 8.2 V to 5.4 V terminal voltage discharge curve, while a single cell Li-ion batteries produce 4.1 V to 2.7 V through out its discharge cycle with a 3.6 V nominal voltage. The discharge curves of Li-ion batteries are very flat when compared to lead acid or alkaline types. Li-ion batteries do not exhibit the memory effects associated with NiCd batteries or the high self discharge rates associated with NiMH batteries.
Hardware Considerations 4.11 Power for the Intel® StrongARM SA-1110 Development Board The following two sections provide a background on the design considerations for the 3.3 V supply on the SA-1110 Development Board and the actual implementation used. 4.11.1 Note: 3.3 V Main System Power Design Considerations This section provides a background on design considerations for the power supply on the SA-1110 Development Board, while Section 5.21.2 describes the actual implementation.
Hardware Considerations LDO cutout point. The efficiency goes up in sleep mode where the small load results in an even lower drop out voltage of 20 mV, which allows the battery to discharge to 3.32 V before drop out starts. With a 3.32 V battery voltage, the 3.3 V LDO linear regulator is over 99% efficient. In addition, using a LDO linear regulator provides the 3.3V rail results with a very clear power supply that requires fewer and smaller filter capacitors, saving cost and board space.
Hardware Considerations wired in parallel with a MIC5219 3.3V LDO which is powered directly from the battery. The MIC5219 has a very low drop out voltage, has an enable input, and is available in very small packaging. With the two LDO outputs wired in parallel, the load is powered from the LDO that has the highest output voltage. As long as the battery is above 3.45 V, the MIC5219 3.3 V LDO powers the 3.3 V circuits on the SA-1110 Development Board. If the battery sags below 3.45 V, then the 3.
Hardware Considerations 4.11.2.2 Virtual Backup Battery The linear boost bootstrap design relies on an LDO regulator in parallel with a boost converter and a post LDO regulator to automatically load switch as the battery voltage falls from a high of 4.1 V down to the 3.45 V main LDO drop out voltage. Below the 3.45 V main LDO drop out, the 3.3 V circuits are powered by the 3.2 V LDO, which is powered from the boost regulator at the 5.5 V.
Hardware Considerations Figure 4-2. Linear Boost Bootstrap Power System 0.33 F SuperCap Li-ion 4.1 V to 2.7 V SA_PWR_EN BATT LOCKOUT 5.5 V Radio Power or 3.5 V During Sleep MAX 1705 track off LDO 3.3 V MAX 1602 LDO 3.2 V 5.0 V LCD Power LDO 5.0 V 3.3 V Main 1.5 V Core A7297-01 4.11.2.4 Radio Power The SA-1110 Development Board supports CDMA or GSM radio module daughter boards. The CDMA board electro-mechanical interface is supported on the SA-1110 Development Board radio connector.
Hardware Considerations 4.11.2.5 LCD Power The Sharp 3.9” LCD requires +5.0 V, +3.3 V +15 V, -14 V, and -11.7 V, all at low or very low power levels. A MAX633 boost switching regulator is used to provide +15 V and to provide a charge pump driver to allow the generation of a –14 V, and from that a 3.3 V Zener diode drops it to –11.7 V. All LCD interfaces require proper sequencing of their power pins. To achieve the sequencing, the SA-1110 Development Board powers all LCD circuits from a MIC5219 5.
Hardware Considerations 4.12 Audio Systems The SA-1110 Development Board audio subsystem has two primary components: the UCB1300 POTS and handset codec and the UDA1341 stereo codec. The UCB1300 is interfaced to the SA1110 Multimedia Communications Port (MCP) and supports POTS softmodem and medium quality mono audio. The UDA1341 is interfaced to the SA-1110 Serial Peripheral Interface (SPI) with the addition of a small amount of glue logic. The UDA1341 supports high quality stereo capture and playback.
Hardware Considerations • Software control of audio destinations • Any OS managed digital audio streams or analog audio source to mini-speaker or UBC microphone input or radio microphone input or headset or headphones • Automatic gain control for microphone1 inputs • Treble, bass and volume control 4.12.1 Stereo Codec A Philips UDA1341 I2S 16 bit delta sigma stereo codec is provided on the SA-1110 Development Board through the glue logic to the SA-1110 SSP port.
Hardware Considerations 4.12.3 Stereo Codec Interface The UDA1341 interfaces to the SA-1110 SSP port. The SSP must be configured in a TI synchronous serial format with 16 bit data slots. A small amount of glue logic is required to interface the UDA1341 to the SSP port. Figure 5-3 shows a simplified version of the glue. The logic is implemented in the SA-1110 Development Board control CPLD. Figure 4-3. Stereo Codec Glue Logic Divide by 4 11.
Hardware Considerations 4.12.4 Microphone and Speaker The SA-1110 Development Board includes two built in electret type microphones as well as a mini speaker. Two microphones are required to provide optimal sound capture. One microphone is used during dictation when the SA-1110 Development Board is held like a tape recorder in front of the mouth. The other microphone is used during voice cell-phone calls when the SA-1110 Development Board is held like a phone.
Hardware Considerations UDA1341 Line1 input right channel analog input mixer as well as to the 2.5 mm headset jack. This allows the UCB1300 to directly drive the phone headset as well as an additional input to the audio mixing functions in the UDA1341 and SA-1110. 4.12.7 Audio System Routing and Mixing Diagram Figure 5-5 provides a guide to managing the audio routing and mixing. The UDA1341 allows mixing of the Line 1 and Line 2 inputs.
Hardware Considerations A second UDA1341 and a standard AC97 codec are also implemented on the SA-1111 Development Module. Figure 4-5.
Hardware Considerations 4.13.1 CDMA Radio Module The SA-1110 Development Board provides primary support for a CDMA radio module. A 30-pin header provides a serial port interface, analog audio input and output, radio control signals and interrupts with a high-power 5.5 V rail. The SA-1110 serial port 3 is used to communicate with the radio modules. CDMA AT modem commands are issued over this interface and data packets are transmitted and received. 4.13.
Hardware Considerations 4.16 USB Slave Port The SA-1110 Development Board includes a standard USB slave jack that allows the SA-1110 Development Board to communicate up to 12 Mbs as a USB slave. This port may be used for high speed system synchronization between the SA-1110 Development Platform and a host PC. The USB port may also supply up to 500 mA of current at 5 V for use by the SA-1110 Development Board.
5 Analog I/O The SA-1110 Development Board has several analog I/O systems in addition to the audio systems. The non-audio analog IO functions include the following: • • • • • 5.1 Battery temperature Battery voltage Charger voltage Spare analog input Touch screen UCB1300 Analog IO The UCB1300 supports four general-purpose analog inputs to the same ten-bit analog to digital converter that support the touch screen. The inputs are high level inputs with 8 V DC required for a full-scale reading.
Analog I/O The single cell Li-Ion battery has critical voltage thresholds as follows: Table 5-2. Battery Voltage Level Indications 2 cell Li-Ion Voltage UCB1300 ADC decimal value (estimated) 2.7V 270 Bottom Of Charge (BOC)—Must not fall below this voltage or battery service life may diminish. 3.0V 300 Sleep Threshold Voltage (STV)—10% charge remaining. Force into sleep mode or data may be lost. 4.1V 410 Top Of Charge (TOC)—Must not exceed this voltage (stop charging immediately). >4.
Analog I/O 5.2 Analog Outputs The SA-1111 Development Platform’s SA-1111 companion chip provides two Pulse Width Modulated (PWM) general purpose outputs. These signals are available as test points on the SA1111 Development Module and are wired to the 140 pin connectors. The PWM signals are intended for use in controlling the brightness and contrast of a display system and are not used in the SA1110 Development Board but may be used by the GFX graphics boards.
System Power Management 6 The SA-1110 Development Board is a battery-powered design. It will also run from an AC adapter that charges the built in batteries or it can draw power from the USB slave port connection. System power management is a complicated resource management problem that requires knowledge of all the system resources, as well as an understanding of battery technology and safety issues.
System Power Management A second battery threshold circuit, a MAX812 chip set to 3.08 V is used to force the SA-1110 system into sleep mode. This signal drives the VDD_FAULT input on the SA-1110. When this interrupt occurs there is no time for user warnings or a user-friendly shutdown. The system is forced into sleep mode. The state of charge on Li-ion cells may be measured with reasonable accuracy simply by measuring the battery terminal voltage and temperature while imposing a consistent load.
System Power Management 6.2.2 Smart Battery Management The SA-1110 Development Board’s battery pack connector includes connections for SMBus smart battery system. Smart battery chips and smart battery packs are attached to the SA-1110 Development Board’s battery pack connector. Smart battery system software has also been developed using this interface. For more information on smart battery systems, refer to Intel’s web site for developers. 6.2.
System Power Management An added complication with sophisticated battery management systems and Li-ion batteries is the possibility of battery fires or explosions caused by flawed hardware or software design or computer viruses. 6.2.6 Fuel Gauging Fuel gauging or gas gauging refers to the hardware and software techniques that attempt to maintain an accurate accounting of the remaining battery capacity. In the past these attempts have proved very inaccurate.
System Power Management • Max charge current • Max temp 6.2.7 Special Handling and Storage Requirements for Batteries The following URL contains battery safety information: Note: The link that follows is provided for your convenience. This link is not part of Intel’s Web site. Intel does not control the content on other company’s Web sites or endorse other companies supplying products or services. http://www.batteryeng.com/safety.
CPLD Code A This appendix lists the CPLD code used on the Intel® StrongARM® SA-1110 Development Board. Note: A.1 These code listing are for reference only. See Intel’s web site for developers to obtain the latest source code. ASSCNTL_P2.PHD File Contents Here are the contents of the asscntl.phd file: module Asscntlp2 title ’Xbus control chip for SA1110’ " " " Copyright © 1999 Intel Corp.
CPLD Code RD_nWR pin 18; SA_PCE1n pin 19; SA_PCE2n pin 20; VX_OEn pin 22; SA_A25 pin 23; CS0n CS1n CS2n CS3n CS4n CS5n pin pin pin pin pin pin 25; 27; 28; 30; 31; 33; SWAP_FLASH pin 37 ; CF_ENAB pin 34; "BCR_OK is cleared on a cold power up and is set after the BCR "is written the first time.
CPLD Code SDCS_BNK2_DIR_1 node ; SDCS_BNK2_DIR_2 node ; SDCS_BNK2_DIR_3 node ; NO_TEST node ; "Node for tri-state enable used in tester MBGNT_CF_IRQ pin 2; "----------------------------------------------------"Clock OE and reset equations "----------------------------------------------------Equations "BCR_OK is clocked true (1) at the end of the first write to the BCR BCR_OK.CLK = !BCR_WRn ; SDCS_BNK2_DIR_1.CLK = SDCLK2 ; SDCS_BNK2_DIR_2.CLK = SDCLK2 ; SDCS_BNK2_DIR_3.CLK = SDCLK2 ; SDCS_BNK2_DIR_1.
CPLD Code "and will go true (1) after the BCR is written BCR_OK := 1 ; MBGNT_CF_IRQ = CF_IRQ_LVL2OE & CF_ON & BCR_OK ; !CF_IRQ_LVL2OE = !FL_BNK1_CSn ; !BSR_RDn = RD_nWR & !CS2n & (SA_A25 # CF_ENAB); !BCR_WRn = !RD_nWR & !CS2n & (SA_A25 # CF_ENAB) ; "CF_ON is an internal node to simplify the CF enable logic CF_ON = CF_ENAB & !CF_BUS_ONn & BCR_OK ; "Turn on BCR after first write !BCR_OEn = BCR_OK ; !NEP_REG_CSn = !CS2n & !SA_A25 & !CF_ENAB ; !FL_BNK1_CSn = (!CS1n & !SWAP_FLASH) # (!CS0n & SWAP_FLASH) ; !FL
CPLD Code !VX_CF_OEn = !CF_ENAB # (CF_ON) ; !VX_A3_0_OEn = (!CF_ENAB & !MBGNT_CF_IRQ) # (CF_ON) ; "Add logic to tristate outputs for in circuit test. Use an impossible input "combination to enable tri-state. SWAP_FLASH and CF_ENAB should not be true at the "same time in a non-tester enviorment "NO_TEST = !(SWAP_FLASH & CF_ENAB) ; NO_TEST = 1 ; "Preliminary "Preliminary "Preliminary "Preliminary end Asscntlp2; A.2 LCD_P2.PHD File Contents Here are the contents of the lcd_p2.
CPLD Code " "----------------------------------------------------"Controls "----------------------------------------------------XPLA PROPERTY ’isp on’; XPLA PROPERTY ’tri-state all’; X = .X.
CPLD Code UDA_WS pin 22; "----------------------------------------------------"CF Signals "----------------------------------------------------CF_CD2n pin 90; CF_CD1n pin 41; MBREQ_CF_DET pin 50; NEP_PRESn pin 42; GFX_PRESn pin 52; CF_ENAB pin 48; "----------------------------------------------------"LCD "----------------------------------------------------H_CNT8..H_CNT0 node ; V_CNT8..V_CNT0 node ; E_CNT8..E_CNT0 node ; HORZ = [H_CNT8..H_CNT0] ; VERT = [V_CNT7..V_CNT0] ; ENAB_CNT = [E_CNT8..
CPLD Code SA_VCLK pin 75; SA_ENAB pin 76; ENAB1 node ISTYPE ’reg_d’ ; ENAB2 node ISTYPE ’reg_d’ ; TV_CLK pin 49; X1 node ISTYPE ’reg_d’ ; X2 node ISTYPE ’reg_d’ ; LCD_SPS pin 100; LCD_CLS pin 99; LCD_LP pin 98; LCD_SPL pin 97; LCD_LBR pin 6; LCD_SPR pin 14; LCD_UBL pin 85; REV pin 12; LCD_PS pin 5; LCD_CLK pin 16; LCD_MODE pin 83; CLK_GATE node ISTYPE ’reg_d’ ; LCD16DATA pin 77; LCD_PWR_ON pin 78; MODE3..
CPLD Code SA_PWR_EN pin 80; SA_PWR_ENn pin 31; AUDIO_PWR_ON pin 81; "----------------------------------------------------"Clock OE and reset equations "----------------------------------------------------Equations ST_SCALER.CLK = IN_CLK ; ST_SCALER.AR = !CODEC_RESETn ; FRACT.CLK = IN_CLK ; FRACT.AR = !CODEC_RESETn ; FLAG.CLK = IN_CLK ; FLAG.AR = !CODEC_RESETn ; FS256CLK.CLK = IN_CLK ; FS256CLK.AR = !CODEC_RESETn ; FS64CLK.CLK = IN_CLK ; FS64CLK.AR = !CODEC_RESETn ; UDA_WS.CLK = !SFRM ; UDA_WS.
CPLD Code LCD_BLU.OE = LCD_PWR_ON ; LCD_SPS.OE LCD_CLS.OE LCD_LP.OE LCD_UBL.OE LCD_LBR.OE LCD_SPR.OE LCD_SPL.OE REV.OE LCD_PS.OE LCD_CLK.OE = = = = = = = = = = LCD_PWR_ON LCD_PWR_ON LCD_PWR_ON LCD_PWR_ON LCD_PWR_ON 0 ; LCD_PWR_ON LCD_PWR_ON LCD_PWR_ON LCD_PWR_ON ; ; ; ; ; ; ; ; ; LCD_SPS.CLK = !SA_PCLK ; LCD_CLS.CLK = !SA_PCLK ; LCD_LP.CLK = !SA_PCLK ; "LCD_UBL.CLK = !SA_PCLK ; "LCD_LBR.CLK = !SA_PCLK ; "LCD_SPR.CLK = !SA_PCLK ; LCD_SPL.CLK = !SA_PCLK ; "LCD_PS.CLK = !SA_PCLK ; REV.
CPLD Code & (FRACTlo !=2) & (FRACTlo !=3)) & (ST_SCALER==^b0000)); "ST_SCALER := (ST_SCALER <= ^b01000) " & (ST_SCALER + 1 + ((FRACTlo !=0) & (FRACTlo !=3)) & (ST_SCALER==^b0010)); SRXD = (UDA_DATO & !LOOPBACK) # (STXD & LOOPBACK) ; UDA_DATI = (STXD & !LOOPBACK) # (UDA_DATO & LOOPBACK) ; UDA_BCLK = !SCLK ;"Output FS32CLK from SA1110 UDA_WS := !UDA_WS ; "Toggle word select on each frame "LCD data paths and timing control "--------------------------------HORZ := (HORZ + 1) ; VERT := (VERT + (HORZ == ^h1)) ;
CPLD Code LCD_SPR LCD_SPL = 1 ; := ENAB1 & !ENAB2 ; "Note that the total number of lines must be an odd number "so that the phase of REV alternates frame to frame.
CPLD Code " "Equations " "State machine counts 5 Vertical pulses before enabling LCD " STATE_DIAGRAM[MODE3,MODE2,MODE1,MODE0] state mode0:if (SA_VCLK & LCD_PWR_ON) then mode1 else mode0; state mode1:if (!SA_VCLK) then mode2 else mode1; state mode2:if (SA_VCLK) then mode3 else mode2; state mode3:if (!SA_VCLK) then mode4 else mode3; state mode4:if (SA_VCLK) then mode5 else mode4; state mode5:if (!SA_VCLK) then mode6 else mode5; state mode6:if (SA_VCLK) then mode7 else mode6; state mode7:if (!SA_VCLK) then mo
In-Circuit Programming B This appendix lists the vendors that support in-circuit programming of Flash devices and CPLDs. Since many new vendors provide in-circuit programming solutions each year, Intel recommends that designers contact them for their latest products. B.1 In-Circuit Programming of Flash Devices The vendors that support in-circuit programming of Flash devices are: JTAG Technologies BV P.O.
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