Specifications

CA1 Course Notes
Sharp Electronics (UK) Limited
CE Technical Support Group Page 53
Data Communication
Figure 46 : CA1 Data Communication
To enable the receiver to work correctly it is necessary to provide some form of communication between
the microprocessor and the NVM and IC201. This is provided by a single I C bus from pins 43 ( SDA ) and
2
54 ( SCL ) of IC1001. This configuration is considerably simpler than that of the CA10 chassis.
A clock is provided at 18MHz to control the internal processing of IC1001. If this clock stops, then the
receiver will not work ( dead ).
IC1001 is divided up into a number of processing sections, one of these will contain the ROM that instructs
the microprocessor. Therefore, it is important to order the correct microprocessor if it should fail. For
example, a microprocessor fitted to a 37DM23H will not work in the text version of this set, the 37ST25H.