Specifications

CA10 Course Notes
Sharp Electronics (UK) Limited
CE Technical Support Group Page 29
The vertical output stage used in the CA10 chassis is based around two field effect transistors - Q501 and
Q502. As power consumption and therefore heat generation needs to be kept to a minimum a class D
amplifier type configuration is utilised. This basically means that the FET’s are used as switches to switch
either the +15V or -15V into the output load ( in this case a low pass filter ) then into the vertical scanning
coils. This is based upon the fact that the input signal from the drive amplifier is a pulse width modulated
signal whose base frequency is 140kHz.
Transistors Q503 and Q504 ensure that the drive signal present at the junction of Q503 emitter and the
collector of Q501 ( marked as point A in the circuit diagram on the next page ), swings between -14.4V
and +4.4V. When the drive signal is high ( positive ), Q503 will be turned on and point A will be +4.4V.
When the drive signal is low ( negative ) then Q504 will turn on and point A will be -14.4V. This is
necessary to ensure that the output FET’s are operating in their fully saturated states, if they were not fully
saturated then the circuit would become inefficient and heat would be generated eventually resulting in
the failure of the FET’s.
Note that D511 ensures that the voltage on the collector ofQ505 does not exceed 6.8V as any voltage
greater than this will damage the device. Q503 and Q504 are emitter followers and as such their emitters
will follow the base voltage, therefore if there is too large a volt drop across the collector/emitter junctions
of these transistors they will fail.
When point A is at +4.4V, the zener diode D504 will be forward biased and therefore current will flow from
the -15V supply via D513 and R505. The gate of Q502 will rise to -6.8V and turn it on and effectively
connect the -15V supply to the output load. At this time the other FET, Q501 will be turned off as its gate
will be +15V by the pull up action of R504 and D512 ( D503 is not conducting ).
When point A changes to -14.4V, Q502 will turn off as D504 ceases to conduct and its gate voltage will
drop to -14.4V by the action of the pull down of R505 and D513. At the same time, D503 will become
forward biased resulting in a voltage of +7.6V on the gate of Q501 which is enough to turn it on and
connecting the +15V supply into the load.
It is vitally important that both Q501 and Q502 are not turned on at the same time as excessive current
will flow between the positive and negative fifteen volt lines resulting in the FET’s going short circuit and
the supply feeds going open circuit. To ensure that this does not occur, each FET needs to be held off
momentarily until the other one has stopped conducting. This is achieved by the capacitors connected
across D503 and D504.
When Q501 is conducting, the voltage on the gate of Q502 will be held at -15V, keeping it turned off. As
the polarity of point A changes and Q501 is turned off, C523 will retain enough charge to hold the gate of
Q502 at -14.4V until Q501 is turned fully off. The reverse occurs when Q502 turns off, but this time
capacitor C506 is used to keep Q501 off. This happens as it takes a small amount of time to charge each
capacitor during the cycle, therefore if the value of the capacitor goes down, or one goes open circuit, the
FET’s would over heat or in worst case expire. By holding off the conduction of Q501 and Q502
momentarily cross over distortion will occur. In a conventional amplifier this is undesirable as it will cause
distortion in the output signal. However, as the output signal passed through a low pass filter to recover
the original frame scanning signal, this cross over distortion can be ignored, i.e. it has no effect on the
drive signal.
From the source of Q502/drain of Q501 the amplified pulse width modulated drive signal passes into a
low pass filter comprising of L504, L505, C502, L502 and C504. This has the effect of removing the
oscillation of 140kHz and leaves the vertical drive signal at 50Hz. This voltage is now fed into the vertical
scanning coils via the socket assembly.
Note that as the positive and negative fifteen volt supplies are generated by the line stage, there will be
no frame scan until the line stage has come up.