Specifications

CA10 Course Notes
Sharp Electronics (UK) Limited
CE Technical Support GroupPage 14
Data communication
Within the CA10 chassis, there are a number of data control signals that pass to and from the main system
microprocessor, IC101. There are two basic types, serial and parallel as shown in the diagram below.
Figure 13 : Data Communication of IC101
I C bus
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There are two I C buses used to communicate serial information to and from IC101. SDA1 and SCL1 is
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used to communicate with IC106 ( Teletext processor ), IC305 ( Audio Processor ), IC201 ( IF, signal and
time base processor ) and the tuner. Each feed is current limited from the processor by the use of
resistors ( except for the teletext processor which is connected directly ). Isolating these lines can be
useful for fault finding - see the I C bus line disconnection section of these notes for more details.
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The other I C bus is used for exclusive communication with the non volatile memory, IC104. IC104
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contains all the user default values such as tuning information and picture control settings as well as
geometry settings, grey scale information, chassis operating characteristics ( text, NICAM etc ). As this
IC may be corrupted by glitches on the communication lines, D113 and D114 are used to suppress any
spikes greater than 5.6 volts that may appear on the clock and data lines.
Parallel communication
Parallel communication exists between the EPROM and the microprocessor. The EPROM is where the
main programme to run the various functions of the set are held eg Text programme, NICAM programme.
As it is necessary for the processor to have fast access to this data, it is connected via a sixteen bit
address line. The data is carried on an eight bit line.